ADSP-BF561

Internal (Core) Supply Voltage¹  (V_DDINT)           0.3 V to +1.4 V
External (I/O) Supply Voltage¹  (V_DDEXT)             0.3 V to +3.8 V
Input Voltage¹                                                     0.5 V to 3.6 V
Output Voltage Swing¹                                        0.5 V to V_DDEXT+0.5 V
Load Capacitance^1,2                                            200 pF
Core Clock (CCLK)¹   
    ADSP-BF561SKBCZ600                                     600 MHz
    ADSP-BF561SKBCZ500                                     500 MHz
System Clock (SCLK)¹                                          133 MHz
Storage Temperature Range¹                             65 to +150
Junction Temperature Under Bias                        125
Lead Temperature (5 seconds)¹                          185oC


¹.Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.


².For proper SDRAM controller operation, the maximum load capacitance is 50 pF (at 3.3V) or 30 pF (at 2.5V) for ADDR25-2, DATA31-0, ABE3-0/SDQM3-0, CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS.