ADSP-TS201S

The ADSP-TS201S TigerSHARC processor is an ultra-high performance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blocks-supporting 32- and 40-bit floating-point and supporting 8-, 16-, 32-, and 64-bit fixed-point processing-to set a new standard of performance for digital signal processors. The TigerSHARC static superscalar architecture lets the DSP execute up to four instructions each cycle, performing twenty-four 16-bit fixed-point operations or six floating-point operations.

Four independent 128-bit wide internal data buses, each connecting to the six 4M bit memory banks, enable quad-word data, instruction, and I/O accesses and provide 28G bytes per second of internal memory bandwidth. Operating at 500 MHz, the ADSP-TS201S processor's core has a 2.0 ns instruction cycle time. Using its Single-Instruction, Multiple-Data (SIMD) features, the ADSP-TS201S processor can perform four billion 40-bit MACs or one billion 80-bit MACs per second. Table 1 shows the DSP's performance benchmarks.