ADSP-TS202S General Description
The ADSP-TS202S TigerSHARC processor is an ultra-high per- formance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blockssupporting 32- and 40-bit floating-point and support ing 8-, 16-, 32-, and 64-bit fixed-point processingto set a new standard of performance for digital signal processors. The TigerSHARC static superscalar architecture lets the DSP exe- cute up to four instructions each cycle, performing twenty-four 16-bit fixed-point operations or six floating-point operations.
Four independent 128-bit wide internal data buses, each con- necting to the six 2Mbit memory banks, enable quad-word data, instruction, and I/O accesses and provide 28Gbytes per second of internal memory bandwidth. Operating at 500MHz, the ADSP-TS202S processors cor has a 2.0ns instruction cycle time. Using its Single-Instruction, Multiple-Data (SIMD) fea- tures, the ADSP-TS202S processor can perform four billion 40- bit MACs or one billion 80-bit MACs per second. Table1 shows the DSP,s performance benchmarks
ADSP-TS202S Maximum Ratings
Internal (Core) Supply Voltage (VDD ) 1 -0.3 V to +1.40V
Analog (PLL) Supply Voltage (VDD_A)1 -0.3 V to +1.40V
External (I/O) Supply Voltage (VDD_IO)1 -0.3 V to +3.5V
External (DRAM) Supply Voltage (VDD_DRAM)1 -0.3 V to +2.1V
Input Voltage1 -0.5 V to 3.63V
Output Voltage Swing1 -0.5 VDD_IO+0.5 V
Storage Temperature Range1 -65 to +150
1Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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