ADSP-TS202S

Features:

·500MHz, 2.0ns Instruction Cycle Rate
·12MBits of InternalOn-Chip-DRAM Memo 25×25mm (576-Ball) Thermally Enhanced Ball Grid Array Package
·Dual Computation Blocks-EachContaining an ALU, a Multi- plier, a Shifter, and a Register File
·Dual Integer ALUs, providing Data Addressing and Pointer  Manipulation
·Integrated I/O Includes 14Channel DMA Controller, External Port, Four Link Ports, SDRAM Controller, Programmable  Flag Pins, Two Timers, and Timer Expired Pin for System  Integration
·1149.1 IEEE Compliant JTAG Test Access Port for On-Chip  Emulation
·On-Chip Arbitration for Glueless Multiprocessing

 

Specifications

Internal (Core) Supply Voltage (V_DD ) ¹                -0.3 V to +1.40V  
Analog (PLL) Supply Voltage (V_{DD_A})¹                   -0.3 V to +1.40V   
External (I/O) Supply Voltage (V_{DD_IO})¹                -0.3 V to +3.5V  
External (DRAM) Supply Voltage (V_{DD_DRAM})¹        -0.3 V to +2.1V 
Input Voltage¹                                                        -0.5 V to 3.63V  
Output Voltage Swing¹                                           -0.5 V_{DD_IO}+0.5 V   
Storage Temperature Range¹                                 -65 to +150


¹Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device  reliability.



Description

The ADSP-TS202S TigerSHARC processor is an ultra-high per- formance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation  blockssupporting 32- and 40-bit floating-point and support ing 8-, 16-, 32-, and 64-bit fixed-point processingto set a new standard of performance for digital signal processors. The  TigerSHARC static superscalar architecture lets the DSP exe- cute up to four instructions each cycle, performing twenty-four 16-bit fixed-point operations or six floating-point operations.

Four independent 128-bit wide internal data buses, each con- necting to the six 2Mbit memory banks, enable quad-word  data, instruction, and I/O accesses and provide 28Gbytes per  second of internal memory bandwidth. Operating at 500MHz,  the ADSP-TS202S processors cor has a 2.0ns instruction cycle time. Using its Single-Instruction, Multiple-Data (SIMD) fea- tures, the ADSP-TS202S processor can perform four billion 40- bit MACs or one billion 80-bit MACs per second. Table1 shows  the DSP^,s performance benchmarks