ADSP21msp58

The ADSP21msp58 combines the ADSP-2100 base architecture (three computation units, data address generators, and program sequencer) with two serial ports, a host interface port, an analog front end, a programmable timer, extensive interrupt capability, and on-chip program and data memory. The ADSP-21msp58 mixed-signal processors (M SProcessor@ SPs) are fully integrated, single-chip SPs complete with a high performance analog front end. The ADSP-21msp58/59 integrates a high performance analog codec based on a single chip, voice band codec, the AD28msp02. The ADSP-21msp58/59 family is optimized for voice band applications such as speech compression, speech processing, speech recognition, text-to speech, and speech-to-text conversion. The ADSP-21msp58 provides 2K words (24 bit) of program RAM and 2K words (16-bit) of data memory. TheADSP21msp58 provides an additional 4K words (24-bit) of program ROM. Powerdown circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-21msp58/59 is available in a 100-pin TQFP package (thin quad flat package). In addition, the ADSP21msp58/59 supports new instructions, which include bit manipulations-bit set, bit clear, bit toggle, bit test-new ALU constants, new multiplication instruction (x squared), biased rounding, and global interrupt masking. SProcessor is a registered trademark of Analog Devices, Inc.

The features of ADSP21msp58 can be summarized as (1)38 ns instruction cycle time (26 MIPS) from 13.00 Hz crystal; (2)ADSP-2100 family code and function compatible with new instruction set enhanced for bit manipulation instructions, multiplication instructions, biased rounding, and global interrupt masking; (3)2K*24 words of on-chip program memory RAM; (4)2K*16 words of on-chip data memory RAM; (5)4K*24 words of on-chip program memory ROM (ADSP-21msp59 only); (6)8-Bit parallel host interface port; (7)analog interface provides: 16-bit sigma-delta ADC and DAC, programmable gain stages, on-chip anti-aliasing & anti-imaging filters, 8 kHz sampling frequency, 65 dB ADC, SNR and THD, 72 dB DAC, SNR and THD; (8)425 mW typical power dissipation @ 5.0 @ 38ns<1 mW powerdown mode with 100 cycle recovery; (9)dual purpose program memory for both instruction and data storage; (10)independent ALU, ultiplier/accumulator, and barrel shifter computational units; (11)two independent data address generators; (12)powerful program sequencer provides: zero overhead looping, conditional instruction execution; (13)Two double-buffered serial ports with companding, hardware, one serial port (sporto) has automatic data buffering; (14)programmable 16-Bit interval timer with prescaler; (15)programmable wait state generation; (16)automatic booting of internal program memory from byte-wide external memory, EPROM, or through host interface port; (17)stand-alone ROM execution (ADSP-21msp59 only); (18)single-cycle instruction execution; (19)single-cycle context switch; (20)ultifunction instructions; (21)three edge- or level-sensitive external interrupts; (22)low power dissipation in standby mode; (23)100-lead TQFP.

The absolute maximum ratings of ADSP21msp58 are (1)supply voltage: -0.3V to +7V; (2)input voltage: -0.3 V to VDD+0.3 V; (3)output voltage swing:-0.3 V to VDD+0.3 V; (4)operating temperature range (ambient): -40°C to +85°C; (5)storage temperature range: -65°C to +150°C; (6)lead temperature (5 sec): +280°C.(Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional; (7)operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.