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Part Number: AFS1500
Description: The CoreFIR is an Actel FPGA-optimized RTL generator that produces a finite impulse response filter. I...
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AFS1500
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DataSheet
General Description
AFS1500 General Description
The CoreFIR is an Actel FPGA-optimized RTL generator that produces a finite impulse response filter. It implements the DA algorithm to eliminate multiplication for faster and smaller designs. The CoreFIR is a generator which utilizes Actel FPGA's embedded RAM blocks as DA lookup tables (when available) to further reduce the size of the design. The generator also reads the user system clock rate and data sample rate to explore using a folding or serial architecture to further reduce size, especially when the system clock rate is much greater than the data sampling rate. The generator automatically switches to the use of multiple DA lookup tables when the requested FIR filter has a large number of taps. Figure 2 shows the functional block diagram of a generated FIR filter design. More complex designs may contain multiple lookup tables, accumulators, or control sections.
AFS1500 Features
• Core Generator
Executable File Outputs Run-Time Library (RTL)
Code and Testbench Based on Input Parameters
Self-Checking Executable Tests Generated
Output against Algorithm
• Distributed Arithmetic (DA) Algorithm
Multiplier-Free Computation
Low Cost
Optimized for Actel FPGAs
• Folding Architecture to Minimize Design Size
Serialized Computation when System Clock Rate is Faster than the Data Sample Rate
• Efficient Structure Using Embedded RAMs
Lookup Tables Utilize Embedded RAMs
• On-Chip DA Lookup Table Generator for FPGA with Embedded RAMs
• Embedded RAMs Initialized as DA Lookup Table
• DA Lookup Table ROM Synthesis for FPGA without Embedded RAMs
• Multiple DA lookup Tables to Split Large Number of Taps
• Actel FPGA-Optimized RTL Code
• Supports 2 to 128 Taps
• 1- to 32-Bit Input Data and Coefficient Precision
Executable File Outputs Run-Time Library (RTL)
Code and Testbench Based on Input Parameters
Self-Checking Executable Tests Generated
Output against Algorithm
• Distributed Arithmetic (DA) Algorithm
Multiplier-Free Computation
Low Cost
Optimized for Actel FPGAs
• Folding Architecture to Minimize Design Size
Serialized Computation when System Clock Rate is Faster than the Data Sample Rate
• Efficient Structure Using Embedded RAMs
Lookup Tables Utilize Embedded RAMs
• On-Chip DA Lookup Table Generator for FPGA with Embedded RAMs
• Embedded RAMs Initialized as DA Lookup Table
• DA Lookup Table ROM Synthesis for FPGA without Embedded RAMs
• Multiple DA lookup Tables to Split Large Number of Taps
• Actel FPGA-Optimized RTL Code
• Supports 2 to 128 Taps
• 1- to 32-Bit Input Data and Coefficient Precision
AFS434S3
PDF/DataSheet Download
- Datasheet: AFS434S3
- File Size: 107709 KB
- Manufacturer: ETC [ETC]
- Click here to Download
- ·AFS8600
- 463714 KB
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