AL5DA134

The asynchronous dual-port SRAMs allow fully independent access to any memory location from both ports without the need of an additional discrete logic. There are separate address, data and control signals for each port. They can be utilized as either a standalone 8/9/16/18-bit dual-port static RAM or as a MASTER/SLAVE cascade form in systems requiring 32/36-bit or greater word widths through pin M/S . Master and slave devices provide two independent ports with separate control, address and I/O pins that permit independent, error-free and asynchronous access for reads and writes to any location in the memory. It is the solution for applications requiring shared or buffered data such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable ( R/W), and output enable (OE ). In addition, a Busy, Interrupt or Semaphore logic may be provided to block the port trying to access the same cell location currently being accessed by the other port. The AL5DAxxxx series are high speed asynchronous CMOS dual-port SRAMs configured as

· 1K/2K x 8-bit organization (AL5DA002/3; Master; Busy Interrupt;3.3V or 5.V)
· 2Kx8-bit organization (AL5DA132; Master; Busy; 3.3V or 5.V)
· 4Kx8-bit organization (AL5DA134; 3.3V or 5.V)
· 4Kx8-bit organization (AL5DA004; Semaphore; 3.3V or 5.V)
· 4Kx8-bit organization (AL5DA138; Master/Slave; Busy Interrupt Semaphore; 3.3V or 5.V)
· 8K/16K/32Kx8-bit organization (AL5DA005/6/7; Master/Slave; Busy Interrupt Semaphore; 3.3V or 5.V)
· 2Kx9-bit organization (AL5DA013; Master; Busy Interrupt; 3.3V or 5.V)
· 4Kx9-bit organization (AL5DA139; Master/Slave; Busy Interrupt Semaphore; 3.3V or 5.V)
· 8K/16K/32Kx9-bit organization (AL5DA015/6/7; Master/Slave; Busy Interrupt Semaphore; 3.3V or 5.V)
· 2Kx16-bit organization (AL5DA023; Master; Busy; 3.3V or 5.V)
· 4K/8K/16Kx16-bit organization (AL5DA024/5/61; Master/Slave; Busy Interrupt Semaphore; 3.3V or 5.V)
· 16Kx16-bit organization (AL5DA026; Master/Slave; Busy Semaphore; 3.3V or 5.V)
· 4K/8K/16Kx18-bit organization (AL5DA034/5/6; Master/Slave; Busy Interrupt Semaphore, 3.3V or 5.V)
· 1Kx8-bit organization (AL5DA140; Slave; Busy Interrupt; 3.3V or 5.V)
· 2Kx8-bit organization (AL5DA142; Slave; Busy; 3.3V or 5.V)
· 2Kx8-bit organization (AL5DA421; Slave; Busy Interrupt; 3.3V or 5.V)
· 2Kx9-bit organization (AL5DA125; Slave; Busy Interrupt; 3.3V or 5.V)
· 2Kx16-bit organization (AL5DA143; Slave; Busy; 3.3V or 5.V)
For more information regarding AL5DAxxxx asynchronous Dual-Port SRAM or other AverLogic products, please contact us, your local authorized representatives or visit our web site.