ALD2502

The ALD1502/ALD2502 timers are high performance single/dual monolithic timing circuits built with advanced silicon gate CMOS technology. They offer the benefits of high input impedance, thereby allowing smaller timing capacitors and a longer timing cycle; high speed, with typical cycle time of 400ns; low power dissipation for battery operated environment; reduced supply current spikes, allowing smaller and lower cost decoupling capacitors.

Each timer is capable of producing accurate time delays and oscillations in both monostable and astable operation, and operates in the one-shot (monostable) mode or 50% duty cycle free running oscillation mode with a single resistor and one capacitor. The inputs and outputs are fully compatible with CMOS, NMOS or TTL logic.

There are three matched internal resistors (approximately 200KW each) that set the threshold and trigger levels at two-thirds and one-third respectively of V+. These levels can be adjusted by using the control terminal. When the trigger input is below the trigger level, the output is in the high state and sourcing 2mA. When the threshold input is above the threshold level at the same time the trigger input is above the trigger level, the internal flip-flop is reset, the output goes to the low state and sinks up to 10mA. The reset input overrides all other inputs and when it is active (reset voltage less than 1V), the output is in the low state.