AM186CU-50KCW

The AM186CU-50KCW is one member of the AM186CU series.The Am186CU USB microcontroller is a cost-effective,high-performance microcontroller solution for communications applications.This highly integrated microcontroller enables customers to save system costs and increase performance over 8-bit microcontrollers and other 16-bit microcontrollers.The microcontroller offers the advantages of the x86development environment's widely available native development tools, applications, and systemsoftware.Additionally, the microcontroller uses the industry-standard 186 instruction set that is part of the AMD E86(TM) family, which continually offers instruction-set-compatible upgrades.

Features of the AM186CU-50KCW are:(1)fourteen chip selects (8 peripherals, 6 memory); (2)external bus mastering support; (3)multiplexed and nonmultiplexed address/data bus; (4)programmable bus sizing; (5)8-bit boot option; (6)three programmable 16-bit timers; (7)hardware watchdog timer; (8)general-purpose DMA (4 channels); (9)programmable I/O (48 PIO signals); (10)interrupt controller (36 maskable interrupts); (11)software migration (backwards-and upwards-compatible); (12)world-class development tools, applications, and system software.

The absolute maximum ratings of the AM186CU-50KCW can be summarized as:(1)temperature under bias industrial:-40 to 85;(2)storage temperature:-65 to 150;(3)voltage on 5-V-tolerant pins with respect to ground:-0.5 to Vcc+2.6V;(4)voltage on other pins with respect to ground:-0.5 to Vcc+0.5V;(5)sustained PIO current on any supply (Vcc) pin:40mA.Although NMI is the highest priority hardware interrupt source, it does not participate in the priority resolution process of the maskable interrupts. There is no bit associated with NMI in the interrupt in-service or interrupt request registers. This means that a new NMI request can interrupt an executing NMI interrupt service routine. As with all hardware interrupts, the interrupt flag (IF) is cleared when the processor takes the interrupt, disabling the maskable interrupt sources. However, if maskable interrupts are re-enabled by software in the NMI interrupt service routine (for example, via the STI instruction), the fact that an NMI is currently in service does not have any effect on the priority resolution of maskable interrupt requests. For this reason, it is strongly advised that the interrupt service routine for NMI should not enable the maskable interrupts.