AS7C31026B-10TC

The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words× 16 bits. It is designed for memory applications where fast data access, low power, and si mple interfacing are desired.Equal address access and cycle times (t_AA, t_RC, t_WC) of 10/12/15/20 ns with output enable access times (t_OE) of 5, 6, 7, 8 ns are ideal forhigh-performance applications.When CEis high, the device enters standby mode.
 
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Dataon the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention,external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips drive I/O pinswith the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in hi gh-impedance mode.

The device provides multiple center power  and ground pins, and separate byte enable controls, allowing individual bytes to be written andread.LB controls the lower bits, I/O0 through I/O7, and BU controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from asingle 3.3 V supply. The device is packaged in common industrystandard packages.