AS7C32096A

The AS7C32096A is a high-performance CMOS 2,097,152-bit Static Random Access Memory (SRAM) device organized as 262,144 words * 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access of AS7C32096A and cycle times (t_AA, t_RC, t_WC) of 10/12/15/20 ns with output enable access times (t_OE) of 4/5/6/7 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems.

When CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power  onsumption in CMOS standby mode.

A write cycle of AS7C32096A is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1I/O8 is written on the rising edge of WE (write cycle 1) orCE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip of AS7C32096A drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3V supply voltage. AS7C32096A is available as per industry standard 44-pin TSOP 2 package