AS7C32098A

The AS7C32098A is a high-performance CMOS 2,097,152-bit Static Random Access Memory (SRAM) device organized as 131,072 words * 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access of AS7C32098A and cycle times (t_AA, t_RC, t_WC) of 10/12/15/20 ns with output enable access times (t_OE) of 4/5/6/7 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank
memory systems.

When CE AS7C32098A is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1I/O16 is written on the rising edge of WE (write cycle 1) or CEAS7C32098A (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) AS7C32098Aand chip enable (CE)AS7C32098A , with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.

The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1I/O8, and UB controls the higher bits, I/O9I/O16.

All chip of AS7C32098A inputs and outputs are TTL- and CMOS-compatible, and operation is for 3.3V (AS7C32098A) supply. The device is available in the JEDEC standard TSOP 2 package