AS7C33512NTD36A

The AS7C33512NTD32A/36A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory(SRAM) organized as 524,288 words × 32 or 36 bits and incorporates a LATE LATE Write.

This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD^TM) architecture, featuring an enhancedwrite operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data,command, and address are all applied to the device on the same clock edge. If a read commandfollows AS7C33512NTD36A write command,the system of AS7C33512NTD36A must wait for two 'dead' cycles for valid data to become available. These dead cycles of AS7C33512NTD36A can significantly reduceoverall bandwidth for applications requiring random access or read-modify-write operations.

NTD^TMAS7C33512NTD36A devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined orone-cycle  flow-through read latency. Write data is applied two cycles after the write command and address, allowing the readpipeline to clear. With NTD^TM, write and read operations of AS7C33512NTD36A can be used in any order without producing dead bus cycles.

Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full32/36 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data isapplied to the device two clock cycles later. Unlike some asynchronous SRAMs, output of AS7C33512NTD36A enable OE does not need to be toggledfor write operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined mode, a two cycle deselect latency of AS7C33512NTD36A allows pending read or writeoperations to be completed.

Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chipselect, R/W pins are ignored, and internal address counters increment in the count sequence specified by theLBO control. Anydevice operations, including burst, can be stalled using the CEN =1, the clock enable input.

The AS7C33512NTD32A/36A operates with a 3.3V ± 5% power supply for the device core (V_DD). DQ circuits use a separatepower supply (V_DDQ) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin TQFP package.