AS7C3513

Features:

• AS7C513 (5V version)
• AS7C3513 (3.3V version)
• Industrial and commercial temperature
• Organization: 32,768 words * 16 bits
• Center power and ground pins
• High speed
   - 12/15/20 ns address access time
   - 6,7,8 ns output enable access time
• Low power consumption: ACTIVE
   - 800 mW (AS7C513) / max @ 12 ns
   - 432 mW (AS7C3513) / max @ 12 ns
• Low power consumption: STANDBY
   - 28 mW (AS7C513) / max CMOS
   - 18 mW (AS7C3513) / max CMOS
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• 44-pin JEDEC standard package
   - 400 mil SOJ
   - 400 mil TSOP II
• ESD protection 2000 volts
• Latch-up current 200 mA


Pinout




Specifications

Parameter	Device	Symbol	Min	Max	Unit
Voltage on VCC relative to GND	AS7C513	Vt1	0.50	+7.0	V
	AS7C3513	Vt1	0.50	+5.0	V
Voltage on any pin relative to GND		Vt2	0.50	VCC +0.50	V
Power dissipation		PD		1.0	W
Storage temperature (plastic)		Tstg	65	+150	°C
Ambient temperature with VCC applied		Tbias	55	+125	°C
DC current into outputs (low)		IOUT		50	mA

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.


Description

The AS7C513 and the AS7C3513 are high performance CMOS 524,288-bit Static Random Access Memory (SRAM) devices organized as 32,768 words * 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access and cycle times (t_AA, t_RC, t_WC) of 12/15/20 AS7C3513 ns with output enable access times (t_OE) of 6,7,8 ns are ideal for high performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems.

When CE is high, AS7C3513 enter standby mode. The AS7C513 and AS7C3513 are guaranteed not to exceed 28/18 mW power consumption in CMOS standby mode. The devices also offer 2.0V data retention.

A write cycle is accomplished by asserting write enable (WE), (UB) and/or (LB), and chip enable (CE). Data on the input pins I/O0-I/O7, and/or I/O8I/O15, is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE), (UB) and (LB), and chip enable (CE), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, or (UB) and (LB), output drivers stay in high-impedance mode.

AS7C3513 provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read.LB controls the lower bits, I/O0I/O7, and UB controls the higher bits, I/O8I/O15.

All chip inputs and outputs are TTL-compatible. The AS7C513 and AS7C3513 are packaged in common industry standard packages.