ASM4SSTVF32852

The 24-Bit to 48-Bit ASM4SSTVF32852 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels except for the LVCMOS RESETB input.

Data flow from D to Q is controlled by the differential clock (CLK/CLKB) and a control signal (RESETB). The positive edge of CLK is used to trigger the data flow,and CLKB is used to maintain sufficient noise margins,whereas the RESETB, an LVCMOS asynchronous signal is intended for use at the time of power-up only.

The ASM4SSTVF32852 supports a low power standby mode of operation. A logic "Low" level at RESETB,assures that all internal registers and outputs (Q) are reset to a logic "Low" state, and that all input receivers,data (D) buffers, and clock (CLK/CLKB) are switched off. Please note that RESETB must always be supported with a LVCMOS levels at a valid logic state since VREF may not be stable during power-up.

To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic "Low" level during power-up.

In the DDR DIMM application, RESETB is specified to be asynchronous with respect to CLK/CLKB. Therefore,no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,the register will be cleared and the outputs will be driven to a logic "Low" level quickly relative to the time to disable the differential input receivers. This ensures there are no "glitches" on any output. However, when coming out of low power standby state, the register will become active quickly relative to the time taken to enable the differential input receivers. When the data inputs are at a logic level "Low" and the clock is stable during the "Low-to-High" transition of RESETB until the input receivers are fully enabled, the design ensures that the outputs will remain at a logic "Low" level.