AT24C02BN-SH-T

The AT24C02BN-SH-T is one member of the AT24C02B series.It has the following features including (1)schmitt trigger, filtered inputs for noise suppression;(2)write protect pin for hardware data protection;(3)partial page writes are allowed;(4)bidirectional data transfer protocol;(5)8-lead JEDEC SOIC and 8-lead TSSOP packages.

The AT24C02B provides 2048 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 256 words of 8 bits each. The AT24C02BN-SH-T is optimized for use in many automotive applications where low-power and low-voltage operation are essential. The AT24C02B is available in space-saving 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a two-wire serial interface. In addition, the entire family is available in 2.5V (2.5V to 5.5V) versions.Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. AT24C02BN-SH-T is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

The AT24C02B has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following table.The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. AT24C02BN-SH-T address stays valid between operations as long as the chip power of AT24C02BN-SH-T is maintained. The address "roll over"during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page.A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition.