AT24C128BN-SH-T

The AT24C128BN-SH-T has thirteen features.(1)low-voltage and standard-voltage operation 1.8 (VCC = 1.8 to 5.5V).(2)internally Organized as 16,384 x 8.(3)two-wire serial interface.(4)schmitt trigger, filtered inputs for noise suppression.(5)bidirectional data transfer protocol.(6)1 MHz (5V, 2.5V), 400 kHz (1.8V) compatibility.(7)write protect pin for hardware and software data protection.(8)64-byte page write mode (partial page writes allowed).(9)self-timed write cycle (5 ms max).(10)high-reliability.(11)lead-free/halogen-free .(12)8-lead JEDEC PDIP, 8-lead JEDEC SOIC, EIAJ SOIC, 8-lead ultra thin small array package (SAP), 8-lead TSSOP, and 8-ball dBGA2 packages.(13)die sales: wafer form, waffle pack, and bumped wafers.

The AT24C128BN-SH-T provides 131,072 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 16,384 words of 8 bits each. The device's cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini MAP, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is available in a 1.8V (5.5V to 3.6V) version.