AT24C64-10PU-2.7

The AT24C64-10PU-2.7 is one member of the AT24C64 series.The AT24C64 provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits each.The device's cascadable feature allows up to 8 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential.

Features of the AT24C64-10PU-2.7 are:(1)internally organized 4096 x 8, 8192 x 8; (2)2-wire serial interface; (3)schmitt trigger, filtered inputs for noise suppression; (4)bidirectional data transfer protocol ; (5)100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) compatibility ; (6)write protect pin for hardware data protection; (7)32-byte page write mode (partial page writes allowed); (8)self-timed write cycle (10 ms max); (9)automotive grade and extended temperature devices available; (10)8-Pin JEDEC PDIP, 8-pin and 14-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin TSSOP packages.The AT24C64 is available in space saving 8-pin JEDEC PDIP, 8-pin and 14-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin TSSOP packages and is accessed via a 2-wire serial interface.In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V),2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.

The absolute maximum ratings of the AT24C64-10PU-2.7 can be summarized as:(1)maximum operating voltage:6.25V;(2)storage temperature:-65 to 150;(3)operating temperature:-55 to +125;(4)voltage on any pin with respect to ground:-1.0V to +7.0VV;(6)DC output current:5.0mA.Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read.