Features: • Complies with Intel® Low-Pin Count (LPC) Interface Specification Revision 1.1
Supports both Firmware Hub (FWH) and LPC Memory Read and Write Cycles
• Auto-detection of FWH and LPC Memory Cycles
Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets
Can Be Used as LPC Flash for Non-Intel Chipsets
• Flexible, Optimized Sectoring for BIOS Applications
32-Kbyte Top Boot Sector, Two 8-Kbyte Sectors, One 16-Kbyte Sector,Seven 64-Kbyte Sectors
Or Memory Array Can Be Divided Into Eight Uniform 64-Kbyte Sectors for Erasing
• Two Configurable Interfaces
FWH/LPC Interface for In-System Operation
Address/Address Multiplexed (A/A Mux) Interface for Programming during Manufacturing
• FWH/LPC Interface
Operates with the 33 MHz PCI Bus Clock
5-signal Communication Interface Supporting Byte Reads and Writes
Two Hardware Write Protect Pins: TBL for Top Boot Sector and WP for All Other Sectors
Five General-purpose Input (GPI) Pins for System Design Flexibility
Identification (ID) Pins for Multiple Device Selection
Sector Locking Registers for Individual Sector Read and Write Protection
• A/A Mux Interface
11-pin Multiplexed Address and 8-pin Data Interface
Facilitates Fast In-System or Out-of-System Programming
• Single Voltage Operation
3.0V to 3.6V Supply Voltage for Read and Write Operations
• Industry-Standard Package Options
32-lead PLCC
40-lead TSOPPinout
SpecificationsVoltage on Any Pin ...................-0.5V to +VCC + 0.5V(1)(2)
Notes: 1. All specified voltages are with respect to GND. During transitions, this level may undershoot to -2.0V for periods of <20 ns.During transitions, this level may overshoot to VCC + 2.0V for periods <20 ns.
2. Do not violate processor or chipset limitations on the INIT pin.
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
DescriptionThe AT49LH004 is a Flash memory device designed for use in PC and notebook BIOS applications. The device complies with version 1.1 of Intel's LPC Interface Specification, providing support for both FWH and LPC memory read and write cycles. The device can also automatically detect the memory cycle type to allow the AT49LH 004 to be used as a FWH with Intel chipsets or as an LPC Flash with non-Intel chipsets.
The sectoring of the AT49LH004's memory array has been optimized to meet the needs of today's BIOS applications. By optimizing the size of the sectors, the BIOS code memory space can be used more efficiently. Because certain BIOS code modules must reside in their own sectors by themselves, the wasted and unused memory space that occurred with previous generation BIOS Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional BIOS routines to be developed and added while still maintaining the same overall device density.
The memory array of the AT49LH004 can be sectored in two ways simply by using two different erase commands. Using one erase command allows the device to contain a total of 11 sectors comprised of a 32-Kbyte boot sector, two 8-Kbyte sectors, a 16-Kbyte sector, and seven 64-Kbyte sectors. The 32-Kbyte boot sector is located at the top (uppermost) of the device's memory address space. Alternatively, by using a different erase command, the memory array can be arranged into eight even erase sectors of 64-Kbyte each.
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The AT49LH004 supports two hardware interfaces: The FWH/LPC interface for In-System operations and the A/A Mux interface for programming during manufacturing. The Interface Configuration (IC) pin of the device provides the control between these two interfaces. An internal Command User Interface (CUI) serves as the control center between the device interfaces and the internal operation of the nonvolatile memory. A valid command sequence written to the CUI initiates device automation.
Specifically designed for use in 3-volt systems, the AT49LH004 supports read, program, and erase operations with a supply voltage range of 3.0V to 3.6V. No separate voltage is required for programming and erasing.
The AT49LH004 utilizes fixed program and erase times, independent of the number of program and erase cycles that have occurred. Therefore, the system does not need to be calibrated or correlated to the cumulative number of program and erase cycles.
AT49LH004 Data Sheet
