AT76C505A

Features:

• Integrates the IEEE 802.11b Physical Layer (Baseband) and the Media Access Controller (MAC) for Supporting Standard Rates up to 11 Mbps
• Supports Antenna Diversity Algorithm, Automatic Receive Gain Control, Transmit Gain Control, Transmit Filter for Japanese Regulatory and Differential or Single-Ended I- and Q-Baseband Signals
• Integrates 160 KBytes of SRAM Organized in Five Banks of 32 KBytes Each, Offering the Flexibility for individually Configuring Each of Them as Program or Data Memory
• Zero Wait States for Program Execution
• Fast Data Transfers through DMA Channels
• Low Power ARM7TDMI^® RISC Processor
• Integrates a Bootstrap ROM Supporting Device Firmware Upgrade (DFU) Protocol and USB Chapter 9 Compatibility
• The Bootstrap Code Supports External SPI EEPROM for the Custom Configuration Parameters Used during the Device Enumeration Phase as well as Default Parameters for First Time EEPROM Programming
• Glueless Parallel Flash Memory Interface, Supporting up to 128 KBytes of Nonvolatile Memory
• Glueless External SRAM Interface for All MAC Operations, Supporting up to 128 KBytes of External Memory
• Wired Equivalency Privacy (WEP) in Hardware Supporting 64-bit and 128-bit Keys
• Hardware Implementation of TKIP
• Hardware Implementation of AES Encryption Supporting Various Modes (CCM/CTR/CBC)
• The WLAN Functions Can Be Easily Changed or Updated to New Requirements Since They are Implemented in Microcode
• Supports 11 Mbps Rates With Automatic Fallback to 5.5, 2 and 1 Mbps
• SPI Interface and 9 GPIO Pins
• 144-ball LFBGA Package
• Low-voltage 1.8V Core Operation



Description

The AT76C505A is a single-chip baseband controller that can handle IEEE 802.11b standard compliant data rates of up to 11 Mbps and provides all processing and functionality needed for the MAC protocol of IEEE 802.11b. The AT76C 505A is a full speed USB 2.0 compliant device that can support up to four configurable Endpoints (EP) plus one Control EP. The AT76C505A USB interface can support Suspend and Resume bus condition for saving power during host idle periods.

Besides the USB interface, the AT76C505A contains a WEP/TKIP engine block, an AES engine block, a MAC Support Unit (MSU), a 802.11b baseband controller, two memory controllers and the ARM^® subsystem consisting of an Interrupt Controller, two 32-bit timers, and an address decoder unit.

The AT76C505A ARM7TDMI core supports two alternative instruction sets. Powerful 32-bit code can be executed by the processor in ARM operating mode. However, a 16-bit instruction subset is also available in Thumb^® mode. Thumb mode can be selected to exploit full processor power with limited external memory resources. Note that ARM7TDMI operating mode can be changed at run time with negligible overhead.