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MFG:ATMEL D/C:08+
Part Number: AT91SAM7XC256
MFG: ATMEL
D/C: 08+
Description: Atmel's AT91SAM7XC256/128 is a member of a series of highly integrated Flash microcontrollers based on...
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AT91SAM7XC256
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General Description
AT91SAM7XC256 General Description
Atmel's AT91SAM7XC256/128 is a member of a series of highly integrated Flash microcontrollers based on the 32-bit ARM RISC processor. It features 256/128 Kbyte high-speed Flash and 64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC, a CAN controller, an AES 128 Encryption accelerator and a Triple Data Encryption System. A complete set of system functions minimizes the number of external components. The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserve its confidentiality.
The AT91SAM7XC256/128 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator.
By combining the ARM7TDMI processor with on-chip Flash and SRAM, and a wide range of peripheral functions, including USART, SPI, CAN Controller, Ethernet MAC, AES 128 accelerator, TDES, Timer Counter, RTT and Analog-to-Digital Converters on a monolithic chip, the AT91SAM7XC256/128 is a powerful device that provides a flexible, cost-effective solution to many embedded control applications requiring secure communication over, for example, Ethernet, CAN wired and Zigbee wireless networks.
AT91SAM7XC256 Features
• Incorporates the ARM7TDMI® ARM® Thumb® Processor
High-performance 32-bit RISC Architecture
High-density 16-bit Instruction Set
Leader in MIPS/Watt
Embedded ICE In-circuit Emulation, Debug Communication Channel Support
• Internal High-speed Flash
256 Kbytes (AT91SAM7XC256) Organized in 1024 Pages of 256 Bytes
128 Kbytes (AT91SAM7XC128) Organized in 512 Pages of 256 Bytes
Single Cycle Access at Up to 30 MHz in Worst Case Conditions
Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
Page Programming Time: 6 ms, Including Page Auto-erase,
Full Erase Time: 15 ms
10,000 Write Cycles, 10-year Data Retention Capability,
Sector Lock Capabilities, Flash Security Bit
Fast Flash Programming Interface for High Volume Production
• Internal High-speed SRAM, Single-cycle Access at Maximum Speed
64 Kbytes (AT91SAM7XC256)
32 Kbytes (AT91SAM7XC128)
• Memory Controller (MC)
Embedded Flash Controller, Abort Status and Misalignment Detection
• Reset Controller (RSTC)
Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout
Detector
Provides External Reset Signal Shaping and Reset Source Status
• Clock Generator (CKGR)
Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
• Power Management Controller (PMC)
Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and
Idle Mode
Four Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt
Protected
• Debug Unit (DBGU)
2-wire UART and Support for Debug Communication Channel interrupt,
Programmable ICE Access Prevention
• Periodic Interval Timer (PIT)
20-bit Programmable Counter plus 12-bit Interval Counter
• Windowed Watchdog (WDT)
12-bit key-protected Programmable Counter
Provides Reset or Interrupt Signals to the System
Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
• Real-time Timer (RTT)
32-bit Free-running Counter with Alarm
Runs Off the Internal RC Oscillator
• Two Parallel Input/Output Controllers (PIO)
Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
Input Change Interrupt Capability on Each I/O Line
Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
• Seventeen Peripheral DMA Controller (PDC) Channels
• One Advanced Encryption System (AES)
128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications
Buffer Encryption/Decryption Capabilities with PDC
• One Triple Data Encryption System (TDES)
Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications
Optimized for Triple Data Encryption Capability
• One USB 2.0 Full Speed (12 Mbits per second) Device Port
On-chip Transceiver, 1352-byte Configurable Integrated FIFOs
• One Ethernet MAC 10/100 base-T
Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)
Integrated 28-byte FIFOs and Dedicated DMA Channels for Transmit and Receive
• One Part 2.0A and Part 2.0B Compliant CAN Controller
Eight Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter
• One Synchronous Serial Controller (SSC)
Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
I²S Analog Interface Support, Time Division Multiplex Support
High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)
Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation
Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
Full Modem Line Support on USART1
• Two Master/Slave Serial Peripheral Interfaces (SPI)
8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
• One Three-channel 16-bit Timer/Counter (TC)
Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• One Four-channel 16-bit Power Width Modulation Controller (PWMC)
• One Two-wire Interface (TWI)
Master Mode Support Only, All Two-wire Atmel EEPROMs Supported
• One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os
• SAM-BA™ Boot Assistance
Default Boot program
Interface with SAM-BA Graphic User Interface
• IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
• 5V-tolerant I/Os, Including Four High-current Drive I/O lines, Up to 16 mA Each
• Power Supplies
Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components
3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply
1.8V VDDCORE Core Power Supply with Brownout Detector
• Fully Static Operation: Up to 55 MHz at 1.65V and 85°C Worst Case Conditions
• Available in a 100-lead LQFP Green Package
High-performance 32-bit RISC Architecture
High-density 16-bit Instruction Set
Leader in MIPS/Watt
Embedded ICE In-circuit Emulation, Debug Communication Channel Support
• Internal High-speed Flash
256 Kbytes (AT91SAM7XC256) Organized in 1024 Pages of 256 Bytes
128 Kbytes (AT91SAM7XC128) Organized in 512 Pages of 256 Bytes
Single Cycle Access at Up to 30 MHz in Worst Case Conditions
Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
Page Programming Time: 6 ms, Including Page Auto-erase,
Full Erase Time: 15 ms
10,000 Write Cycles, 10-year Data Retention Capability,
Sector Lock Capabilities, Flash Security Bit
Fast Flash Programming Interface for High Volume Production
• Internal High-speed SRAM, Single-cycle Access at Maximum Speed
64 Kbytes (AT91SAM7XC256)
32 Kbytes (AT91SAM7XC128)
• Memory Controller (MC)
Embedded Flash Controller, Abort Status and Misalignment Detection
• Reset Controller (RSTC)
Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout
Detector
Provides External Reset Signal Shaping and Reset Source Status
• Clock Generator (CKGR)
Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
• Power Management Controller (PMC)
Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and
Idle Mode
Four Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt
Protected
• Debug Unit (DBGU)
2-wire UART and Support for Debug Communication Channel interrupt,
Programmable ICE Access Prevention
• Periodic Interval Timer (PIT)
20-bit Programmable Counter plus 12-bit Interval Counter
• Windowed Watchdog (WDT)
12-bit key-protected Programmable Counter
Provides Reset or Interrupt Signals to the System
Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
• Real-time Timer (RTT)
32-bit Free-running Counter with Alarm
Runs Off the Internal RC Oscillator
• Two Parallel Input/Output Controllers (PIO)
Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
Input Change Interrupt Capability on Each I/O Line
Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
• Seventeen Peripheral DMA Controller (PDC) Channels
• One Advanced Encryption System (AES)
128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications
Buffer Encryption/Decryption Capabilities with PDC
• One Triple Data Encryption System (TDES)
Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications
Optimized for Triple Data Encryption Capability
• One USB 2.0 Full Speed (12 Mbits per second) Device Port
On-chip Transceiver, 1352-byte Configurable Integrated FIFOs
• One Ethernet MAC 10/100 base-T
Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)
Integrated 28-byte FIFOs and Dedicated DMA Channels for Transmit and Receive
• One Part 2.0A and Part 2.0B Compliant CAN Controller
Eight Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter
• One Synchronous Serial Controller (SSC)
Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
I²S Analog Interface Support, Time Division Multiplex Support
High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)
Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation
Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
Full Modem Line Support on USART1
• Two Master/Slave Serial Peripheral Interfaces (SPI)
8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
• One Three-channel 16-bit Timer/Counter (TC)
Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• One Four-channel 16-bit Power Width Modulation Controller (PWMC)
• One Two-wire Interface (TWI)
Master Mode Support Only, All Two-wire Atmel EEPROMs Supported
• One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os
• SAM-BA™ Boot Assistance
Default Boot program
Interface with SAM-BA Graphic User Interface
• IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
• 5V-tolerant I/Os, Including Four High-current Drive I/O lines, Up to 16 mA Each
• Power Supplies
Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components
3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply
1.8V VDDCORE Core Power Supply with Brownout Detector
• Fully Static Operation: Up to 55 MHz at 1.65V and 85°C Worst Case Conditions
• Available in a 100-lead LQFP Green Package
AT91SAM7XC256
PDF/DataSheet Download
- Datasheet: AT91SAM7XC256
- File Size: 843776 KB
- Manufacturer: ATMEL
- Click here to Download
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