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Part Number: AT94KAL
Description: The AT94KAL Series FPSLIC family shown in Table 1-1 is a combination of the popular Atmel AT40K Series...
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AT94KAL
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DataSheet
General Description
AT94KAL General Description
The AT94KAL Series FPSLIC family shown in Table 1-1 is a combination of the popular Atmel AT40K Series SRAM FPGAs and the high-performance Atmel AVR 8-bit RISC microcontroller with standard peripherals. Extensive data and instruction SRAM as well as device control and management logic are included on this monolithic device, fabricated on Atmel's 0.35 five-layer metal CMOS process.
The AT40K FPGA core is a fully 3.3V PCI-compliant, SRAM-based FPGA with distributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks,Cache Logic ability (partially or fully reconfigurable without loss of data) and 5,000 to 40,000 usable gates.
AT94KAL Features
• Monolithic Field Programmable System Level Integrated Circuit (FPSLIC®)
AT40K SRAM-based FPGA with Embedded High-performance RISC AVR® Core,
Extensive Data and Instruction SRAM and JTAG ICE
• 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM™
2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM
High-performance DSP Optimized FPGA Core Cell
Dynamically Reconfigurable In-System FPGA Configuration Access Available
On-chip from AVR Microcontroller Core to Support Cache Logic® Designs
Very Low Static and Dynamic Power Consumption Ideal for Portable and
Handheld Applications
• Patented AVR Enhanced RISC Architecture
120+ Powerful Instructions Most Single Clock Cycle Execution
High-performance Hardware Multiplier for DSP-based Systems
Approaching 1 MIPS per MHz Performance
C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers
Low-power Idle, Power-save and Power-down Modes
100 A Standby and Typical 2-3 mA per MHz Active
• Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM
Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM
Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
• JTAG (IEEE std. 1149.1 Compliant) Interface
Extensive On-chip Debug Support
Limited Boundary-scan Capabilities According to the JTAG Standard (AVR Ports)
• AVR Fixed Peripherals
Industry-standard 2-wire Serial Interface
Two Programmable Serial UARTs
Two 8-bit Timer/Counters with Separate Prescaler and PWM
One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
Modes and Dual 8-, 9- or 10-bit PWM
• Support for FPGA Custom Peripherals
AVR Peripheral Control 16 Decoded AVR Address Lines Directly Accessible
to FPGA
FPGA Macro Library of Custom Peripherals
• 16 FPGA Supplied Internal Interrupts to AVR
• Up to Four External Interrupts to AVR
• 8 Global FPGA Clocks
Two FPGA Clocks Driven from AVR Logic
FPGA Global Clock Access Available from FPGA Core
• Multiple Oscillator Circuits
Programmable Watchdog Timer with On-chip Oscillator
Oscillator to AVR Internal Clock Circuit
Software-selectable Clock Frequency
Oscillator to Timer/Counter for Real-time Clock
• VCC: 3.0V - 3.6V
• 3.3V 33 MHz PCI-compliant FPGA I/O
20 mA Sink/Source High-performance I/O Structures
All FPGA I/O Individually Programmable
• High-performance, Low-power 0.35 CMOS Five-layer Metal Process
• State-of-the-art Integrated PC-based Software Suite including Co-verification
• 5V I/O Tolerant
• Green (Pb/Halide-free/ROHS compliant) Package Options Available
AT40K SRAM-based FPGA with Embedded High-performance RISC AVR® Core,
Extensive Data and Instruction SRAM and JTAG ICE
• 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM™
2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM
High-performance DSP Optimized FPGA Core Cell
Dynamically Reconfigurable In-System FPGA Configuration Access Available
On-chip from AVR Microcontroller Core to Support Cache Logic® Designs
Very Low Static and Dynamic Power Consumption Ideal for Portable and
Handheld Applications
• Patented AVR Enhanced RISC Architecture
120+ Powerful Instructions Most Single Clock Cycle Execution
High-performance Hardware Multiplier for DSP-based Systems
Approaching 1 MIPS per MHz Performance
C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers
Low-power Idle, Power-save and Power-down Modes
100 A Standby and Typical 2-3 mA per MHz Active
• Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM
Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM
Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
• JTAG (IEEE std. 1149.1 Compliant) Interface
Extensive On-chip Debug Support
Limited Boundary-scan Capabilities According to the JTAG Standard (AVR Ports)
• AVR Fixed Peripherals
Industry-standard 2-wire Serial Interface
Two Programmable Serial UARTs
Two 8-bit Timer/Counters with Separate Prescaler and PWM
One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
Modes and Dual 8-, 9- or 10-bit PWM
• Support for FPGA Custom Peripherals
AVR Peripheral Control 16 Decoded AVR Address Lines Directly Accessible
to FPGA
FPGA Macro Library of Custom Peripherals
• 16 FPGA Supplied Internal Interrupts to AVR
• Up to Four External Interrupts to AVR
• 8 Global FPGA Clocks
Two FPGA Clocks Driven from AVR Logic
FPGA Global Clock Access Available from FPGA Core
• Multiple Oscillator Circuits
Programmable Watchdog Timer with On-chip Oscillator
Oscillator to AVR Internal Clock Circuit
Software-selectable Clock Frequency
Oscillator to Timer/Counter for Real-time Clock
• VCC: 3.0V - 3.6V
• 3.3V 33 MHz PCI-compliant FPGA I/O
20 mA Sink/Source High-performance I/O Structures
All FPGA I/O Individually Programmable
• High-performance, Low-power 0.35 CMOS Five-layer Metal Process
• State-of-the-art Integrated PC-based Software Suite including Co-verification
• 5V I/O Tolerant
• Green (Pb/Halide-free/ROHS compliant) Package Options Available
AT94KAL
PDF/DataSheet Download
- Datasheet: AT94KAL
- File Size: 850668 KB
- Manufacturer: ATMEL
- Click here to Download
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