ATTINY13A-SSU

The ATTINY13A-SSU is one member of the ATTINY13A series.The ATtiny13A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

Features of the ATTINY13A-SSU are:(1)120 powerful instructions most single clock cycle execution; (2)32 x 8 general purpose working registers; (3)fully static operation; (4)up to 20 MIPS througput at 20 MHz; (5)debugWIRE on-chip debug system; (6)in-system programmable via SPI port; (7)external and internal interrupt sources; (8)low power idle, ADC noise reduction, and power-down modes; (9)enhanced power-on reset circuit; (10)programmable brown-out detection circuit with software disable function; (11)internal calibrated oscillator.The ATtiny13A provides the following features: 1K byte of In-System Programmable Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three soft-ware selectable power saving modes.

The absolute maximum ratings of the ATTINY13A-SSU can be summarized as:(1)power supply:1.8 to 5.5V;(2)operation range:-40 to 85.This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.