ATtiny12 General Description
ATtiny12 Features
• Utilizes the AVR® RISC Architecture
• High-performance and Low-power 8-bit RISC Architecture
90 Powerful Instructions Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Up to 8 MIPS Throughput at 8 MHz
• Nonvolatile Program and Data Memory
1K Byte of Flash Program Memory In-System Programmable (ATtiny12) Endurance: 1,000 Write/Erase Cycles (ATtiny11/12)
64 Bytes of In-System Programmable EEPROM Data Memory for ATtiny12 Endurance: 100,000 Write/Erase Cycles
Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
Interrupt and Wake-up on Pin Change
One 8-bit Timer/Counter with Separate Prescaler
On-chip Analog Comparator
Programmable Watchdog Timer with On-chip Oscillator
• Special Microcontroller Features
Low-power Idle and Power-down Modes
External and Internal Interrupt Sources
In-System Programmable via SPI Port (ATtiny12)
Enhanced Power-on Reset Circuit (ATtiny12)
Internal Calibrated RC Oscillator (ATtiny12)
• Specification
Low-power, High-speed CMOS Process Technology
Fully Static Operation
• Power Consumption at 4 MHz, 3V, 25°C
Active: 2.2 mA
Idle Mode: 0.5 mA
Power-down Mode: <1 A
• Packages
8-pin PDIP and SOIC
• Operating Voltages
1.8 - 5.5V for ATtiny12V-1
2.7 - 5.5V for ATtiny11L-2 and ATtiny12L-4
4.0 - 5.5V for ATtiny11-6 and ATtiny12-8
• Speed Grades
0 - 1.2 MHz (ATtiny12V-1)
0 - 2 MHz (ATtiny11L-2)
0 - 4 MHz (ATtiny12L-4)
0 - 6 MHz (ATtiny11-6)
0 - 8 MHz (ATtiny12-8)
ATtiny12 Connection Diagram
Map list: ABCDEFGHIJKLMNOPQRSTUVWXYZ 0123456789All