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AZ100LVEL33

Features: • Green / RoHS Compliant / Lead (Pb) Free package available• Operating Range of 3.0V to 5.5V• 470ps Propagation Delay• 4.0GHz Toggle Frequency• Internal Input Pulldown Resistors• Direct Replacement for ON Semiconductor MC10EL33, MC100EL33, and MC100LVE...

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SeekIC No. : 004293220 Detail

AZ100LVEL33: Features: • Green / RoHS Compliant / Lead (Pb) Free package available• Operating Range of 3.0V to 5.5V• 470ps Propagation Delay• 4.0GHz Toggle Frequency• Internal Input...

AZ100LVEL33 Data Sheet

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Part Number:
AZ100LVEL33
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Green / RoHS Compliant / Lead (Pb) Free package available
• Operating Range of 3.0V to 5.5V
• 470ps Propagation Delay
• 4.0GHz Toggle Frequency
• Internal Input Pulldown Resistors
• Direct Replacement for ON Semiconductor MC10EL33, MC100EL33, and MC100LVEL33
• Transistor Count = 91 Devices
• IBIS Model Files Available on Arizona Microtek Web Site


Specifications

Symbol
 Characteristic
Rating
Unit
VCC
 PECL Power Supply (VEE = 0V)
0 to +6.0
Vdc
VI
 PECL Input Voltage (VEE = 0V)
0 to +6.0
Vdc
VEE
 ECL Power Supply (VCC = 0V)
-8.0 to 0
Vdc
VI
 ECL Input Voltage (VCC = 0V)
-6.0 to 0
Vdc
IHGOUT
Output Current - Continuous
- Surge
50
100
mA
TA
 Operating Temperature Range
-40 to +85
°C
TSTG
 Storage Temperature Range
-65 to +150
°C



Description

The AZ10/100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low, Q¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET allows for the synchronization of multiple LVEL33's in a system.

The LVEL33 provides a VBB output for single-end use or a DC bias reference for AC coupling to the device.

For single-ended input applications, the VBB reference should be connected to one side of the CLK/ C¯¯L¯K¯  ifferential input pair. The input signal is then fed to the other CLK/ C¯¯L¯K¯ input. The VBB pin can support 1.0mA sink/source current. When used, the VBB pin should be bypassed to ground via a 0.01F capacitor.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.




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