Features: ` Data Management Software (DMS)
- AMD-supplied software manages data programming,
enabling EEPROM emulation
- Eases historical sector erase flash limitations
` Supports Common Flash Memory Interface (CFI)
` Erase Suspend/Erase Resume
- Suspends erase operations to allow reading from
other sectors in same bank
` Data# Polling and Toggle Bits
- Provides a software method of detecting the status of
program or erase cycles
` Unlock Bypass Program command
- Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
` Ready/Busy# output (RY/BY#)
- Hardware method for detecting program or erase
cycle completion
` Hardware reset pin (RESET#)
- Hardware method of resetting the internal state
machine to the read mode
` WP#/ACC input pin
- Write protect (WP#) function protects sectors 0, 1,
140, and 141, regardless of sector protect status
- Acceleration (ACC) function accelerates program timing
` Sector protection
- Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that sector
- Temporary Sector Unprotect allows changing data in
protected sectors in-systemPinout
SpecificationsStorage Temperature
Plastic Packages . . . . . . . . . . . . . . 65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . .65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . 0.5 V to +4.0 V
A9, OE#, and RESET#
(Note 2) . . . . . . . . . . . . . . . . . . . . 0.5 V to +12.5 V
WP#/ACC . . . . . . . . . . . . . . . . . . 0.5 V to +10.5 V
All other pins (Note 1) . . . . . . 0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V.
During vol tage transitions, input or I/O pins may
overshoot VSS to 2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 7. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 8.
2. Minimum DC input voltage on pins A9, OE#, RESET#,
and WP#/ACC is 0.5 V. During voltage transitions, A9,
OE#, WP#/ACC, and RESET# may overshoot VSS to
2.0 V for periods of up to 20 ns. See Figure 7. Maximum
DC input voltage on pin A9 is +12.5 V which may
overshoot to +14.0 V for periods up to 20 ns. Maximum
DC input voltage on WP#/ACC is +9.5 V which may
overshoot to +12.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.DescriptionThe Am29DL640G70 is a 64 megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode data appears on DQ15DQ0; byte mode data appears on DQ7DQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers.
Am29DL640G70 is available with an access time of 65, 70, 90, or 120 ns and is offered in 48-pin TSOP, 63-ball Fine-Pitch BGA, and 64-ball Fortified BGA packages. Standard control pins-chip enable (CE#), write enable (WE#), and output enable (OE#)-control normal read and write operations, and avoid bus contention issues.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
Simultaneous Read/Write Operations with Zero Latenc The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks, two 8 Mb banks with small and large sectors, and two 24 Mb banks of large sectors. Sector addresses are fixed, system software can be used to form user-defined bank groups.
During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. Am29DL640G70 can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations.
The Am29DL640G70 can be organized as both a top and bottom boot sector configuration.
Am29DL640G70 Data Sheet
