Am29F004B

The Am29F004B is a 4 Mbit, 5.0 volt-only Flashmemory device organized as 524,288 bytes. The dataappears on DQ0DQ7. The device is offered in a 32-pin PLCC package. This device is designed to be pro-grammed in-system with the standard system 5.0 voltVCC supply. A 12.0 volt VPP is not required for program orerase operations. The device can also be programmed instandard EPROM programmers.

The device offers access times of 55, 70, 90, and 120 ns,allowing high speed microprocessors to operatewithout wait states. To eliminate bus contention eachdevice has separate chip enable (CE#), write enable(WE#) and output enable (OE#) controls.

Each device requires only a single 5.0 volt powersupply for both read and write functions. Internallygenerated and regulated voltages are provided for theprogram and erase operations.

The Am29F004B is entirely command set compatiblewith the JEDEC single-power-supply Flash stan-dard. Commands are written to the command registerusing standard microprocessor write timing. Registercontents serve as inputs to an internal state-machinethat controls the erase and programming circuitry.

Write cycles also internally latch addresses and dataneeded for the programming and erase operations.Reading data out of the device is similar to reading
from other Flash or EPROM devices.Device programming occurs by executing the programcommand sequence. This initiates the EmbeddedProgram algorithm-an internal algorithm that automat-ically times the program pulse widths and verifiesproper cell margin.

Device erasure occurs by executing the erasecommand sequence. This initiates the EmbeddedErase algorithman internal algorithm that automaticallypreprograms the array (if it is not already programmed)before executing the erase operation. During erase, thedevice automatically times the erase pulse widths andverifies proper cell margin.

The host system can detect whether a program orerase operation is complete by reading the DQ7 (Data#Polling), or DQ6 (toggle) status bits. After a programor erase cycle has been completed, the device is readyto read array data or accept another command.

The sector erase architecture allows memory sectorsto be erased and reprogrammed without affecting thedata contents of other sectors. The device is fullyerased when shipped from the factory.Hardware data protection measures include a lowVCC detector that automatically inhibits write operationsduring power transitions. The hardware sector protectionfeature disables both program and erase operations inany combination of sectors of memory. This can beachieved in-system or via programming equipment.

The Erase Suspend feature enables the user to puterase on hold for any period of time to read data from,or program data to, any sector that is not selected forerasure. True background erase can thus be achieved.

The device offers a standby mode as a power-savingfeature. Once the system places the device into thestandby mode power consumption is greatly reduced.AMD's Flash technology combines years of Flashmemory manufacturing experience to produce thehighest levels of quality, reliability and cost effective-ness. The device electrically erases all bits within asector simultaneously via Fowler-Nordheim tunnelling.

The data is programmed using hot electron injection.