Am29F010B

The Am29F010B is a 1 Mbit, 5.0 Volt-only Flash emory organized as 131,072 bytes. The Am29F010B isoffered in 32-pin PDIP, PLCC and TSOP packages. The byte-wide data appears on DQ0-DQ7. The de-vice is designed to be programmed in-system with the tandard system 5.0 Volt VCC supply. A 12.0 volt V PP is notrequired for program or erase operations. The device canalso be programmed or erased in standard EPROMprogrammers.

Thsdevice is manufactured using AMD's 0.32 µm pro-cess technology, and offers all the features and benefits f the Am29F010 and Am29F010A. The standard device offers access times of 45, 55, 70,90, and 120 ns, allowing high-speed microprocessorsto operate without wait states. To eliminate bus conten-tion the device has separate chip enable (CE#), writeenable (WE#) and output enable (OE#) controls.The device requires only a single 5.0 volt power sup-ply for both read and write functions. Internallygenerated and regulated voltages are provided for theprogram and erase operations.

The device is entirely command set compatible with theJEDEC single-power-supply Flash standard. Com-mands are written to the command register usingstandard microprocessor write timings. Register con-tents serve as input to an internal state machine thatcontrols the erase and programming circuitry. Write cycles also internally latch addresses and data neededfor the programming and erase operations. Reading dta out of the device is similar to reading from otherFlash or EPROM devices.Device programming occurs by executing the programcommand sequence. This invokes the EmbeddedProgram algorithm-an internal algorithm that auto-matically times the program pulse widths and verifiesproper cell margin.

Device erasure occurs by executing the erase com-mand sequence. This invokes the Embedded Erasealgorithm-an internal algorithm that automatically pre-programs the array (if it is not already programmed)before executing the erase operation. During erase,the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program orerase operation is complete by reading the DQ7 (Data#Polling) and DQ6 (toggle) status bits. After a programor erase cycle has been completed, the device is readyto read array data or accept another command. The sector erase architectureallows memory sectorsto be erased and reprogrammed without affecting thedata contents of other sectors. The device is erasedwhen shipped from the factory.The hardware data protection measures include alow VCC detector automatically inhibits write operationsduring power transitions. The hardware sector protec-tion feature disables both program and eraseoperations in any combination of the sectors of memory,and is implemented using standard EPROMprogrammers.

The system can place the device into the standby mode.Power consumption is greatly reduced in this mode.AMD's Flash technology combines years of Flash memory manufacturing experience to produce thehighest levels of quality, reliability, and costeffectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheimtunneling. The bytes are programmed one byte at atime using the EPROM programming mechanism of hot electron injection.