Am29LV017M

The Am29LV017M is a 16 Mbit, 3.0 Volt-only Flashmemory organized as 2,097,152 bytes. The device isoffered in 48-ball FBGA and 40-pin TSOP packages.

The byte-wide (x8) data appears on DQ7DQ0. Allread, program, and erase operations are accomplishedusing only a single power supply. The device can alsobe programmed in standard EPROM programmers.

The standard device offers access times of 70, 90, and120 ns, allowing high speed microprocessors tooperate without wait states. To eliminate bus conten-tion the device has separate chip enable (CE#), writeenable (WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power sup-ply for both read and write functions. Internally gener-ated and regulated voltages are provided for theprogram and erase operations.

The device is entirely command set compatible with theJEDEC single-power-supply Flash standard. Com-mands are written to the command register using stan-dard microprocessor write timings. Register contentsserve as input to an internal state-machine that con-trols the erase and programming circuitry. Write cyclesalso internally latch addresses and data needed for theprogramming and erase operations. Reading data outof the device is similar to reading from other Flash orEPROM devices.

Device programming occurs by executing the programcommand sequence. This initiates the EmbeddedProgram algorithm-an internal algorithm that automaticallytimes the program pulse widths and verifiesproper cell margin. The Unlock Bypass mode facilitatesfaster programming times by requiring only twowrite cycles to program data instead of four.

Device erasure occurs by executing the erase commandsequence. This initiates the Embedded Erasealgorithm-an internal algorithm that automatically preprogramsthe array (if it is not already programmed) beforeexecuting the erase operation. During erase, thedevice automatically times the erase pulse widths andverifies proper cell margin.

The host system can detect whether a program orerase operation is complete by observing the RY/BY#pin, or by reading the DQ7 (Data# Polling) and DQ6(toggle) status bits. After a program or erase cyclehas been completed, the device is ready to read arraydata or accept another command.

The sector erase architecture allows memory sectorsto be erased and reprogrammed without affecting thedata contents of other sectors. The device is fullyerased when shipped from the factory.Hardware data protection measures include a lowVCC detector that automatically inhibits write operationsduring power transitions. The hardware sectorprotection feature disables both program and eraseoperations in any combination of the sectors of memory.

This can be achieved in-system or via programmingequipment.The Erase Suspend feature enables the user to puterase on hold for any period of time to read data from,or program data to, any sector that is not selected forerasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operationin progress and resets the internal state machine toreading array data. The RESET# pin may be tied to thesystem reset circuitry. A system reset would thus alsoreset the device, enabling the system microprocessorto read the boot-up firmware from the Flash memory.

The device offers two power-saving features. Whenaddresses have been stable for a specified amount oftime, the device enters the automatic sleep mode.The system can also place the device into the standbymode. Power consumption is greatly reduced in boththese modes.AMD's Flash technology combines years of Flashmemory manufacturing experience to produce thehighest levels of quality, reliability and cost effectiveness.

The device electrically erases all bits withina sector simultaneously via Fowler-Nordheim tunneling.The data is programmed using hot electron injection.