Am29LV200B

The Am29LV200B is a 2 Mbit, 3.0 volt-only Flash memory organized as 262,144 bytes or 131,072 words.
The device is offered in 44-pin SO and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15¨CDQ0; the byte-wide (x8) data appears on DQ7-DQ0. This device is designed to be programmed in- system using only a single 3.0 volt V_CC supply.No V_PPis required for write or erase operations. The device can also be programmed in standard EPROM pro- grammers.
This device is manufactured using AMD!s 0.35um process technology, and offers all the features and ben- efits of the Am29LV200, which was manufactured using 0.5 ?m process technology. In addition, the Am29LV200B features unlock bypass programming and in-system sector protection/unprotection.
The standard device offers access times of 70, 80, 90 and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally gener-ated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Com-mands are ritten to the command register using standard microprocessor write timings. Register con-tents serve as input to  n internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch  ddresses and data needed for the programming and erase operations. Reading data out of the device is similar to eading rom other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program lgorithm!aan internal algorithm that auto matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili-tates faster programming times by requiring only two write cycles to program data nstead of four.
Device erasure occurs by executing the erase com-mand sequence. This initiates the Embedded Erase algorithm!aan internal algorithm that automaticall preprograms the array (if it is not already programmed) before executing the ase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY#pin, or by eading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data ontents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low detector that automatically inhibits write opera-_VCCtions during ower transitions. The hardware sector protection feature disables both program and erase operations in any ombination of the sectors of mem- ory. This can be achieved in-system or via program-ming equipment.
The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or rogram data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When ad-dresses have been stable for a specified amount of time, the device enters the automatic sleep mode.
The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.
AMD!s Flash technology combines years of Flas memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tun-neling. The data is programmed using hot electron injection.