BCM3212

Description

The BCM3212 is a highly integrated CMTS MAC IC for use in DOCSIS 1.1 CMTS products. With hardware support for concatenation parsing, fragment reassembly, Payload Header Suppression, and advanced data rates, the BCM3212 serves as the heart of a next generation CMTS. The BCM3212 provides a powerful yet cost effective solution for a variety of CMTS architectures.

The BCM3212 is based on sophisticated hardware processing engines for both the upstream and downstream paths. The BCM3212 achieve upstream throughput of 200,000 packets per second, the Upstream Processor design is segmented and uses two banks of SDRAM to minimize latency on the internal buses. The Upstream Processor performs DES decryption, fragment reassembly, deconcatenation, Payload Header Expansion, PROPANE packet acceleration, upstream MIB statistic gathering, and priority queuing for the resultant packets. Each upstream queue of BCM3212 may be independently configured to output packets to either the PCI or GMII interface. DOCSIS MAC Management messages and bandwidth requests are extracted and queued separately from data packets so that they are readily available to the system controller.