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Part Number: CB45000
Description: The CB45000 standard cell series uses a high performance, low voltage, 5 level metal, HCMOS6 0.35 micr...
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General Description
CB45000 General Description
The CB45000 standard cell series uses a high performance, low voltage, 5 level metal, HCMOS6 0.35 micron process to achieve subnanosecond internal speeds while offering very low power dissipation and high noise immunity.
With an average routed logic density of 14000 gates/mm2, the CB45000 family allows the design of highly complex devices. The potential available gate count ranges above 3 Million equivalent gates. Devices can operate over a Vdd voltage range of 2.7 to 3.6 volts.
The I/O count for this array family ranges to over 750 signals and 1000 pins based upon the package technology utilized. A flexible I/O approach has been developed to provide an optimum solution for today's complex system problems of drive levels and specialized interface standards.
The product offers a variable bonding approach supporting pad spacings from 80m upwards and supports staggered pad rows to address today's bonding technologies. Additional flexibility to support 65m and 50m pad spacing will be available in the near future.
The I/O can be configured for circuits ranging from low voltage CMOS and TTL to low swing differential circuits (LVDS) and the 1Gigabit per second high speed link. Standards like SCSI, 3.3 and 5 Volt PCI and other 5.0 Volt interfaces are currently being addressed.
CB45000 Maximum Ratings
| Supply Voltage, Vdd | -0.5 V to + 4.6 V |
| Input or Output Voltage 5 Volt Tolerant Input or Output Voltage |
-0.5 V to (Vdd + 0.5V) -0.5 V to +6.0 V |
| DC Forward Bias Current, Input or Output | -24mA source, +24mA sink |
| Storage Temperature Ceramic | -65 to 150 degrees Centigrade |
| Storage Temperature Plastic | -40 to 125 degrees Centigrade |
ote 1. Referenced to Vss. Stresses above those listed under "absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect the device reliability.
Note 2. A dedicated 5V extra power supply is needed in case of PCI buffer usage in order to clip the incoming signal on PCI pads to the
5 Volt tolerant specified Absolute Maximum Rating (5V + Vbe value)R.
CB45000 Features
·0.35 micron 5 layer metal HCMOS6 process, retrograde well technology, low resistance salicided active areas and polysilicide gates.
·3.3 V optimized transistor with 5 V I/O interface capability
·2 - input NAND delay of 160 ps (typ) with fanout = 2.
·Broad I/O functionality including Low Voltage CMOS, Low Voltage TTL and LVDS. Driving capability to ISA, EISA, PCI, MCA, and SCSI interface levels
·High drive I/O; capability of sinking up to 24 mA with slew rate control, current spike suppression and impedance matching.
·Generators to support Single Port RAM, Dual Port RAM, and ROM with BIST options.
·DRAM integration in ASIC methodology
·Extensive embedded function library including ST DSP and micro cores, third party micros and Synopsys synthetic libraries.
·Fully independent power and ground configurations for inputs, core and outputs.
·I/O ring capability up to 1000 pads.
·Latchup trigger current > +/- 500 mA. ESD protection > +/- 4000 volts typical value
·Oscillators for wide frequency spectrum.
·Broad range of 500+ SSI cells
·Design For Test features including IEEE 1149.1 JTAG Boundary Scan architecture.
·Cadence, Mentor and Synopsys based design systems with interfaces from multiple workstations.
·Broad ceramic and plastic package range.
·3.3 V optimized transistor with 5 V I/O interface capability
·2 - input NAND delay of 160 ps (typ) with fanout = 2.
·Broad I/O functionality including Low Voltage CMOS, Low Voltage TTL and LVDS. Driving capability to ISA, EISA, PCI, MCA, and SCSI interface levels
·High drive I/O; capability of sinking up to 24 mA with slew rate control, current spike suppression and impedance matching.
·Generators to support Single Port RAM, Dual Port RAM, and ROM with BIST options.
·DRAM integration in ASIC methodology
·Extensive embedded function library including ST DSP and micro cores, third party micros and Synopsys synthetic libraries.
·Fully independent power and ground configurations for inputs, core and outputs.
·I/O ring capability up to 1000 pads.
·Latchup trigger current > +/- 500 mA. ESD protection > +/- 4000 volts typical value
·Oscillators for wide frequency spectrum.
·Broad range of 500+ SSI cells
·Design For Test features including IEEE 1149.1 JTAG Boundary Scan architecture.
·Cadence, Mentor and Synopsys based design systems with interfaces from multiple workstations.
·Broad ceramic and plastic package range.
CB45000
PDF/DataSheet Download
- Datasheet: CB45000
- File Size: 272358 KB
- Manufacturer: STMICROELECTRONICS [STMicroelectronics]
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- ·CB45000 SERIES
- STMicro
- HCMOS6 STANDARD CELLS
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