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Part Number: CB65000
Description: The CB65000 standard cell series uses a high performance, low-voltage, 0.18 ...
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CB65000
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General Description
CB65000 General Description
The CB65000 standard cell series uses a high performance, low-voltage, 0.18 m drawn, six metal levels, high density and high speed HCMOS8D process.
With an average routed gate density of 85,000 gates/mm2, the CB65000 family allows the integration of up to 30 million equivalent gates and is ideal for high-complexity or high-performance devices for computer, telecommunication and consumer products.
With a gate delay of 35 ps with High Performance transistor and 60 ps with Low Leakage transistor (for a 2-input NAND gate at fan-out 1), the library meets the most demanding speed requirements in telecommunication and
computer application designs today.
Optimized for 1.8 V operation, the library features a power consumption of less than 35 nW/Gate/MHz (High Performance; fan-out=1) and 25 nW/Gate/MHz (Low Leakage; fan-out=1) at 1.8 V.
The I/O buffers can be fully configured for both 1.8 V and 3.3 V interface options, with several high speed buffer types available. These include: low voltage differential (LVDS) I/Os, PCI, AGP, USB, LVTTL, LVCMOS and SSTL.
The pad pitch down to 50 m, in a staggered arrangement, meets the requirements of high pin-count devices which tend to become pad-limited at such library densities. For very high pin-count ICs, advanced solutions such as Ball Grid Array packages are available.
New packaging solutions using a flip-chip approach are currently being developed.
CB65000 Features
` 0.18micron drawn, six layers of metal connected by fully stackable vias and contacts, Shallow Trench Isolation,
low resistance, salicided active areas and gates. Deep UV lithography.
` 1.8 V optimized High Performance and Low Leakage transistors with 3.3 V I/O and supply interface capability.
` Average gate density: 85K/mm2, plus low power consumption of 30nanoWatt/Gate/MHz/ Stdload.
` Two input NAND delay of 35ps with High Performane transistor and 60ps with Low Leakage transistor.
` Library available in commercial, industrial and military temperature range. Power supply ranging from 1.2V
and 1.95V for Core (according to JESD 8-7 specification) and between 3.0V and 3.6V for I/Os (alligned with
JESD 8-A specification).
` Broad I/O functionality including:
` Low Voltage CMOS.
` Low Voltage TTL,HSTL, SSTL.
` AGP 2X and 4X, USB, PCI, LVDS I/O interfaces are also available.
` Drive capability up to 8 mA per buffer with slew rate control, current spike suppression impedance matching,
and process compensation capability to reduce delay variation.
` Designs easily portable from previous generations of CB55000 with an average factor 2 density increase,
30% speed improvement
` and 2.5 power reduction at respective nominal voltages.
` Generators to support Single Port, Dual port and multiple Port RAM, and ROMs with BIST options.
` Extensive embedded function library including ST DSP and micro-cores, third-party IPs, Synopsys and Mentor
I nventra synthetic libraries ideally suited for complete System On Chip fast integration .
` Embedded DRAM Capability
` 80 m pitch linear and 50 m staggered pad libraries.
` Fully independent power and ground configuration for core and I/Os supported.
` I/O ring capability up to 1500 pads.
` Latch-up trigger current > ± 500 mA. ESD protection above 4 kV in H.B.M.
` Oscillators and PLLs for wide frequency spectrum.
` Broad range of more than 600 SSI cells.
` Design for test features including IEEE 1149.1 JTAG Boundary Scan architecture.
` Synopsys, Cadence and Mentor based design systems with interface from multiple workstations.
` Broad range of packaging solutions, including PBGA, LBGA, SBGA, HPBGA, TQFP, PQFP, PLCC up to 1000 pins
with enhanced power dissipation options.
` 1.25 GigaHertzGigabit DLL technique.
low resistance, salicided active areas and gates. Deep UV lithography.
` 1.8 V optimized High Performance and Low Leakage transistors with 3.3 V I/O and supply interface capability.
` Average gate density: 85K/mm2, plus low power consumption of 30nanoWatt/Gate/MHz/ Stdload.
` Two input NAND delay of 35ps with High Performane transistor and 60ps with Low Leakage transistor.
` Library available in commercial, industrial and military temperature range. Power supply ranging from 1.2V
and 1.95V for Core (according to JESD 8-7 specification) and between 3.0V and 3.6V for I/Os (alligned with
JESD 8-A specification).
` Broad I/O functionality including:
` Low Voltage CMOS.
` Low Voltage TTL,HSTL, SSTL.
` AGP 2X and 4X, USB, PCI, LVDS I/O interfaces are also available.
` Drive capability up to 8 mA per buffer with slew rate control, current spike suppression impedance matching,
and process compensation capability to reduce delay variation.
` Designs easily portable from previous generations of CB55000 with an average factor 2 density increase,
30% speed improvement
` and 2.5 power reduction at respective nominal voltages.
` Generators to support Single Port, Dual port and multiple Port RAM, and ROMs with BIST options.
` Extensive embedded function library including ST DSP and micro-cores, third-party IPs, Synopsys and Mentor
I nventra synthetic libraries ideally suited for complete System On Chip fast integration .
` Embedded DRAM Capability
` 80 m pitch linear and 50 m staggered pad libraries.
` Fully independent power and ground configuration for core and I/Os supported.
` I/O ring capability up to 1500 pads.
` Latch-up trigger current > ± 500 mA. ESD protection above 4 kV in H.B.M.
` Oscillators and PLLs for wide frequency spectrum.
` Broad range of more than 600 SSI cells.
` Design for test features including IEEE 1149.1 JTAG Boundary Scan architecture.
` Synopsys, Cadence and Mentor based design systems with interface from multiple workstations.
` Broad range of packaging solutions, including PBGA, LBGA, SBGA, HPBGA, TQFP, PQFP, PLCC up to 1000 pins
with enhanced power dissipation options.
` 1.25 GigaHertzGigabit DLL technique.
CB65000
PDF/DataSheet Download
- Datasheet: CB65000
- File Size: 579600 KB
- Manufacturer: STMicroelectronics
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