CD4520BMS

Features:

• High Voltage Types (20V Rating)
• CD4518BMS Dual BCD Up Counter
• CD4520BMS Dual Binary Up Counter
• Medium Speed Operation
6MHz Typical Clock Frequency at 10V
• Positive or Negative Edge Triggering
• Synchronous Internal Carry Propagation
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
1V at VDD = 5V
2V at VDD = 10V
2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

Application

• Multistage Synchronous Counting
• Multistage Ripple Counting
• Frequency Dividers




Pinout






Specifications

DC Supply Voltage Range, (VDD)..0.5V to +20V (Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs .....................................................-0.5V to VDD +0.5V
DC Input Current, Any One Input.......................................................................±10mA
Operating Temperature Range ................. -55 to +125 Package Types D, F, K, H
Storage Temperature Range (TSTG).................................................. -65 to +150
Lead Temperature (During Soldering) ............................................................. +265
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum




Description

CD4518BMS Dual BCD Up Counter and CD4520BMS Dual Binary Up Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The CD4520BMS counters are cleared by high levels on their RESET lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low.