CD4724BMS

Features:

• High Voltage Type (20V Rating)
• Serial Data Input
• Active Parallel Output
• Storage Register Capability
• Master Clear
• Can Function as Demultiplexer
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
•1V at VDD = 5V
• 2V at VDD = 10V
• 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative StandardNo. 13B, "Standard Specifications for Description of'B'  Series   CMOS Devices"


Application

• Multi-line Decoders
• A/D Converters


Pinout




Specifications

^{_{DC Supply Voltage Range, (VDD) . . . . . . . . . . . .  . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs  . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input  . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range. . . . . . . . . . . . .  -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering)  . . . . . . . . . . . . .  . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for}}
10s Maximum


Description

CD4724BMS 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions.Data are inputted to a particular bit in the latch when that bit isaddressed (by means of inputs A0, A1, A2) and when WRITEDISABLE is at a low level. When WRITE DISABLE is high

dataentry is inhibited; however, all 8 outputs can be continuouslyread independent of WRITE DISABLE and address inputs.
A master RESET input is available, which resets all bits to alogic "0" level when RESET and WRITE DISABLE are at a highlevel. When CD4724BMS RESET is at a high level, and WRITE DISABLE isat a low level, the latch acts as a 1-of-8 demultiplexer; the bitthat is addressed has an active output which follows that datainput, while all unaddressed bits are held to a logic "0" level
The CD4724BMS is supplied in these 16-lead outline pack-ages:
Braze Seal DIP     H4W
Frit Seal  DIP        H1F
Ceramic  Flatpack  H6W