CD54AC109

Specifications

DC Supply Voltage, V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6V
DC Input Diode Current, IIK
    For V_I < -0.5V or V_I > V_CC+ 0.5V . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .±20mA
DC Output Diode Current, I_OK
    For V_O < -0.5V or V_O > V_CC+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current, Per Output Pin, I_O
    For V_O > -0.5V or V_O < V_CC+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
DC V_CCor GND Current, I_CC or I_GND
    For Up to 4 Outputs Per Device, Add ±25mA For Each
    Additional Output . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±100mA
Power Dissipation Per Package, P_D
    T_A = -55 to +100 (Package F) . . . . . . . . . . . . . . ..  . . . . . . . . . . . . . . . . . 500mW
    T_A = +100 to +125 (Package F) . . . . . . . . Derate Linearly at 8mW/ to 300mW
Operating Temperature Range, T_A 
    Package Type F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125
    Storage Temperature, T_STG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150
Lead Temperature (During Soldering)
    At Distance 1/16in. ± 1/32in. (1.59mm ± 0.79mm)
    From Case For 10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265
    Unit Inserted Into a PC Board (Min Thickness 1/16in., 1.59mm)
    With Solder Contacting Lead Tips Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.


Description

The CD54AC109/3A and CD54ACT109/3A are dual "J-K" flip-flops with set and reset that utilize the Harris Advanced CMOS Logic technology. These flip-flops have independent J, K, Set, Reset and Clock inputs and Q and Q outputs. The CD54AC109/3A and CD54ACT109/3A changes state on the positive-going transition of the clock. Set and Reset are accomplished asynchronously by low-level inputs.

The CD54AC109/3A and CD54ACT109/3A are supplied in 16 lead dual-in-line ceramic packages (F suffix).