CGS74C2525

Features:

These CGS devices implement National's FACTTM family
 Ideal for signal generation and clock distribution
 Guaranteed pin to pin and part to part skew
 Multiplexed clock input ('2526)
 Guaranteed 2 kV minimum ESD protection
 Symmetric output current drive of 24 mA for IOL/IOH
 'CT has TTL-compatible inputs
 These products are identical to 74AC/ACT2525 and 2526
 Available as Mil/Aero versions
  54AC/ACT2525
  54AC/ACT2526


Pinout




Specifications

Supply Voltage (V_CC)                                        -0.5V to +7.0V
DC Input Diode Current (I_IK)
V_I=-0.5V                                                                     -20 mA
V_I= V_CC +0.5V                                                          +0.2 mA
DC Input Voltage (V_I)                            -0.5V to (V_CC +0.5V)
DC Output Diode Current (I_OK)
V_O =0.5V                                                                    -20 mA
V_O = V_CC +0.5V                                                         +20 mA
DC Output Voltage (V_O)                        -0.5V to (V_CC +0.5V)
DC Output Source
or Sink Current (I_O)                                                   ±50 mA
DC V_CC or Ground Current
per Output Pin (I_CC or I_GND)                                    g±50 MA
Storage Temperature (T_STG)                         -65 to +150
Junction Temperature (i_JA)
Plastic (N) 14-Lead                                                  102/W
Plastic (M) 14-Lead                                                  128/W
Plastic (N) 16-Lead                                                    97/W
Plastic (M) 16-Lead                                                  124/W



Description

   The CGS 'C/CT2525 is a minimum skew clock driver with one input driving eight outputs specifically designed for signal generation and clock distribution applications. The '2525 is designed to distribute a single clock to eight separate receivers with low skew across all outputs during both the tPLH and tPHL transitions. The '2526 is similar to the '2525 but contains a multiplexed clock input to allow for systems with dual clock speeds or systems where a separate test clock has been implemented.