CH7202

Features:

• Outputs NTSC, PAL (B,D,G,H,I) and PAL-M (NTSCJ or PAL-60 available as options)
• 8-bit YCrCb (4:2:2) input format
• Master or slave mode operation
• Triple 9-bit DAC for composite and S-video output
• 27 MHz DAC operating frequency eliminates the need for 1/sinc(x) correction filter
• Low-jitter phase-locked loop circuitry operates using a low-cost 14.31818 MHz crystal
• 40.5 or 33.9 MHz video decoder clock output
• 16.934 or 11.289 MHz audio decoder clock output
• 13.5 MHz and 27 MHz video pixel clock outputs
• Internal 4.6 MHz (max) luminance and 1.3 MHz chrominance filters
• Sub-carrier genlocked to HSYNC* and VSYNC*
• Sleep mode
• CMOS technology in 44-pin PLCC
• 5V single-supply operation


Pinout




Specifications

Symbol	Description	Min	Typ	Max	Units
	VDD relative to GND	- 0.5		7.0	V
	Input voltage of all digital pins1	GND - 0.5		VDD + 0.5	V
TSC	Analog output short circuit duration		Indefinite		Sec
TAMB	Ambient operating temperature	- 55		125
TSTOR	Storage temperature	- 65		150
TJ	Junction temperature			150
TVPS	Vapor phase soldering (one minute)			220
PMAX	Maximum Power dissipation			TBD	W

Description

The CH7202 video encoder integrates a dual PLL clock generator and a digital NTSC/PAL video encoder. By generating all essential clock signals for MPEG playback, and converting digital video inputs to either NTSC or PAL video signals, the CH7202 is an essential component of any low-cost solution for video-CD playback machines.

The CH7202 dual PLL clock synthesizer generates all clocks and timing signals from a 14.31818 MHz reference crystal (see application note 19 "Tuning Clock Outputs" for selection and tuning of the 14.31818 MHz crystal). The CH7202 will accept HSYNC*, VSYNC*, and 2XPCLK clock inputs during slave mode operation. Timing signals from the PLLs can be used to generate the horizontal and vertical sync signals which enable operating the CH7202 in master mode.

The fully digital video encoder CH7202 is pin-programmable to generate either a 525-line NTSC or a 625-line PAL compatible video signal. It also features a logic selectable sleep mode which turns the encoder off while leaving both PLL's running.