CN8223

Features:

• Integrates 7 line framers with ATM
   layer processing according to ATM
   Forum UNI and NNI Specifications
• UTOPIA Level 1 interface
• Internal framers for DS3, E3 (G.751, G.832), E4 (G.832), STS-1, STS-3c, STM-1
• PLCP and G.804 HEC cell alignment for all data rates from 1.544 Mbps to 155 Mbps
• Direct interface to TAXITM or external T1/E1 framers
• ATM and SMDS cell modes
• 4 FIFO ports with header screening, formatting, and transmit priority controls
• Idle cells generated and screened
• Statistics counts latched on one-second intervals
• Error detection and insertion
• Option insertion or generation of all line and cell overhead
• Serial or parallel line interface
• Available evaluation module reference design and software
• Supports Automatic Protection Switching (APS) 


Application

• WAN equipment
• ATM switches
• Test equipment
• ATM routers and hub


Pinout




Description

The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network (UNI) and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI Specification 94/0317; Bellcore Specifications TR-TSV-000772, TR-TSV-000773, TR-NWT-000253, and T1S1/92-185; ITU Recommendations I.432, G.707, G.751, G.832, and Q.921; and ETSI prETS 300 213 and 300 214. Both Customer Premise Equipment (CPE) and switching system interface functions are provided. The CN8223 provides DS1, E1, DS3, E3, E4, STS-1, and STS-3c (and STM-1) ATM cell alignment functions. The system interface is via a parallel FIFO port or UTOPIA interface. In addition, the CN8223 terminates the operations and maintenance flows F1, F2, and F3.

The CN8223 provides four FIFO port interfaces and one UTOPIA interface. Each receiver port can be programmed with a particular Virtual Channel Identifier/Virtual Path Identifier (VCI/VPI) address for message routing. VCI/VPI pages can also be selected via masking registers.

CN8223 microprocessor can set control registers for insertion of selected header fields by the transmitter on an individual port basis. The microprocessor can also control insertion of all overhead and can insert errors in selected fields for test equipment applications.