CS18LV10245

Features:

1. Fully static operation and Tri-state output
2. TTL compatible inputs and outputs
3. Ultra low power consumption :
`2.0V (min) data retention
` Low operation voltage : 4.5 ~ 5.5V ; 5mA@1MHz (Max.) operating current (Vcc = 5.0V)
4. Standby Typ. = 0.50uA, (Typical value @ Vcc = 5.0V, TA = 25 0C)
5. Standard pin configuration
`32 - SOP 450mil
`32 - sTSOP-I - 8X13.4mm
`32 - TSOP-I 8X20mm
`32 - PDIP 600mil


Pinout




Specifications

Symbol	Parameter	Rating	Unit
VTERM	Terminal Voltage with Respect to GND	-0.5 to Vcc+0.5	V
TBIAS	Temperature Under Bias	-40 to +125
TSTG	Storage Temperature	-60 to +150
PT	Power Dissipation	1.0	W
IOUT	DC Output Current	25	mA

Description

The CS18LV10245 is a high performance, high speed and super low power CMOS Static Random Access Memory organized as 131,072 words by 8bits and operates from a wide range of 4.5 to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed, super low power features and maximum access time of 55/70ns in 5V operation. Easy memory expansion is provided by an active LOW chip enable (/CE) and active LOW output enable (/OE).

The CS18LV10245 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS18LV10245 is available in JEDEC standard 32-pin sTSOP - I (8x13.4 mm), TSOP - I (8x20mm), SOP (450 mil) and PDIP (600 mil) packages.