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Part Number: CS91
Description: The CS91 series 0.11 mm CMOS standard cell is a line of highly integrated CMOS ASICs featuring high sp...
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CS91
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DataSheet
General Description
CS91 General Description
The CS91 series 0.11 mm CMOS standard cell is a line of highly integrated CMOS ASICs featuring high speed and low power consumption. This series incorporates up to 48 million gates which have a gate delay time of 16 ps, resulting in both integration and speed about three times higher than conventional products.
CS91 Maximum Ratings
| Parameter |
Symbol |
Application |
Rating |
Unit | |
|
Min |
Max | ||||
| Power supply voltage |
VDD |
VDDI (Internal) |
VSS - 0.5 |
1.8 |
V |
| VDDE (External 2.5 V) |
VSS - 0.5 |
3.6 |
V | ||
| VDDE (External 3.3 V) |
VSS - 0.5 |
4.0 |
V | ||
| Input voltage*1 |
VI |
1.2 V |
VSS - 0.5 |
VDDI + 0.5 ( 1.8 V) |
V |
| 2.5 V |
VSS - 0.5 |
VDDE + 0.5 ( 3.6 V) |
V | ||
| 3.3 V |
VSS - 0.5 |
VDDE + 0.5 (4.0 V) |
V | ||
| Output voltage |
VO |
1.2 V |
VSS - 0.5 |
VDDI + 0.5 (1.8 V) |
V |
| 2.5 V |
VSS - 0.5 |
VDDE + 0.5 ( 3.6 V) |
V | ||
| 3.3 V |
VSS - 0.5 |
VDDE + 0.5 (4.0 V) |
V | ||
| Storage temperature |
TST |
Plastic package |
-55 |
+125 |
|
| Power-supply pin current *2 |
ID |
Per VDDI/VDDE pin |
-- |
-- |
mA |
| Per VSS pin |
-- |
-- |
mA | ||
| Output current*3 |
IO |
L type simultaneous switching noise : minimum, delay : long |
-- |
-- |
mA |
| M type simultaneous switching noise : small, delay : middle |
-- |
-- |
mA | ||
| H type simultaneous switching noise : middle, delay : short |
-- |
-- |
mA | ||
CS91 Features
• Technology : 0.11 mm silicon-gate CMOS, 5- to 8-layer wiring (Copper is used as wire material.) ,
-Low-K (2.7) Inter-layer material (Inter-layer material that has low permittivity)
• Support for high speed, high integration, low leak internal cell set. Capable of incorporating on the same chip.
• Supply voltage : +1.2 V ± 0.1 V (standard specification)
• Junction temperature range : -40 °C to +125 °C
• Gate delay time : tpd = 16 ps (1.2 V, inverter, F/O = 1)
• Gate power consumption : Pd = 6.6 nW/MHz/BC (1.2 V, inverter, F/O = 1)
• Support for ultra high speed (622 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps, 10 Gbps) interface macros for transmission
• Special interfaces : P-CML, LVDS, PCI, SSTL-2, GTL, TLVTTL, and others. )
• Buffer cell dedicated to crystal oscillator
• IP macros : CPU (ARM9, ARM7TDMI) , DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, and others.
• Compiled cells (RAM/ROM/multiplier, and others.)
• Hardware/software co-design environment
• Short-term development using a timing driven layout tool
• Hierarchical design environment for supporting large-scale circuits
• Support for SIGNAL INTEGRITY, EMI noise reduction
• Support for High resolution RC extraction base delay calculation environment
• Support for optimization environment of power supply wire
• Support for static timing sign off
• Support for memory (RAM) BIST
• Support for boundary SCAN
• Support for LOGIC BIST
• A variety of package options : FC-BGA (2116 pin Max) , EBGA, and others.
-Low-K (2.7) Inter-layer material (Inter-layer material that has low permittivity)
• Support for high speed, high integration, low leak internal cell set. Capable of incorporating on the same chip.
• Supply voltage : +1.2 V ± 0.1 V (standard specification)
• Junction temperature range : -40 °C to +125 °C
• Gate delay time : tpd = 16 ps (1.2 V, inverter, F/O = 1)
• Gate power consumption : Pd = 6.6 nW/MHz/BC (1.2 V, inverter, F/O = 1)
• Support for ultra high speed (622 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps, 10 Gbps) interface macros for transmission
• Special interfaces : P-CML, LVDS, PCI, SSTL-2, GTL, TLVTTL, and others. )
• Buffer cell dedicated to crystal oscillator
• IP macros : CPU (ARM9, ARM7TDMI) , DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, and others.
• Compiled cells (RAM/ROM/multiplier, and others.)
• Hardware/software co-design environment
• Short-term development using a timing driven layout tool
• Hierarchical design environment for supporting large-scale circuits
• Support for SIGNAL INTEGRITY, EMI noise reduction
• Support for High resolution RC extraction base delay calculation environment
• Support for optimization environment of power supply wire
• Support for static timing sign off
• Support for memory (RAM) BIST
• Support for boundary SCAN
• Support for LOGIC BIST
• A variety of package options : FC-BGA (2116 pin Max) , EBGA, and others.
CS91 Series
PDF/DataSheet Download
- Datasheet: CS91 Series
- File Size: 123111 KB
- Manufacturer: Fujitsu
- Click here to Download
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