Features: • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications• Distributes one clock input to one bank of ten outputs• Output enable bank control• External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal• No external...
CSP2510D: Features: • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications• Distributes one clock input to one bank of ten outputs• Output enable bank control• External...
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Clock Drivers & Distribution 10+1 Outputs PLL/Clk Driver
Symbol |
Rating |
Max |
Unit |
VDD | Supply Voltage Range |
0.5 to +4.6 |
V |
VI(1) | Input Voltage Range |
0.5 to +6.5 |
V |
VO(1,2) | Voltage range applied to any output in the high or low state |
0.5 to VDD + 0.5 |
V |
IIK (VI <0) |
Input clamp current |
50 |
mA |
IOK (VO <0 or VO > VDD) |
Terminal Voltage with Respect to GND (inputs VIH 2.5, VIL 2.5) |
±50 |
mA |
IO (VO = 0 to VDD) |
Continuous Output Current |
±50 |
mA |
VDD or GND | Continuous Current |
±100 |
mA |
TSTG | Storage Temperature Range |
65 to +150 |
°C |
TJ | Junction Temperature |
+150 |
°C |