CT3232M

Features:

•1.5 Watt Total Hybrid Dissipation at 25% Transmitting Duty Cycle
•Monolithic Design
•Compatible with MIL-STD-1553A/B & Macair A3818, A5232, A5690 & A4905
•Meets MIL-STD-1553B
•TTL Compatible
•Full Military (-55°C to +125°C) Temperature Range
•Driver / Receiver in a single Package for Space & Weight Savings
•Filtering on Receiver to Improve S/N Ratio of System
•Pin for Pin interchangeable with CT3231 Series
•Packaging Hermetic Metal Plug-In or Flat Package
 .24 Lead, 1.27" sq. max x .2" Ht Flat package
 .24 Pin, 1.27" sq. max x .175" Ht Plug-In package


Pinout




Specifications

Parameter	Range	Units
Supply Voltage, Pin 4 or 13	-0.3 to +18.0	Volts
Supply Voltage, Pin 24 or 19	0.3 to -18.0	Volts
Supply Voltage, Pin 20	-0.3 to + 7.0	Volts
Logic Input Voltage, Pin 8, 21, 22, or 23	-0.3 to +5.5V	Volts
Receiver Differential Input, Pin 15 to Pin 16	±20 (40 Vp-p)	Volts
Receiver Input Voltage, Pin 15 or Pin 16	±15	Volts
Driver Peak Output Current, Pin 1 or Pin 2	±300	mA
Total Package Power Dissipation at (Ambient) TA = + 25°C (Derate above TA = + 25°C at 40 mW/°C)	4.0 (Note 1)	Watts
Power Dissipation at Specified Case Temperatures	See Figure 5
Operating Case Temperature Range (TC) (See Figure 5 for limitations)	-55 to +125	°C

Description

The CT3232 Driver section accepts complementary TTL Data at the input, and produces a 30 Volt nominal peak-to-peak differential signal across a 140 load at the output. When coupled to the Data Bus with a 1:1 transformer, isolated on the Data Bus side with two 55.0 fault isolation resistors, and loaded by two 70 terminations plus additional receivers, the Data Bus signal produced is 7.2 Volts nominal peak-to-peak. When both "DATA" and "DATA" inputs are held low or both are held high, the driver output CT3232M becomes a high impedance and is "removed" from the line. In addition, an overriding "INHIBIT" input provides for removal of the Driver output from the line. A logic "1" applied to the "INHIBIT" takes priority over the condition of the data inputs and disables the Driver. See Driver Logic Waveforms, Figure 3. DATA and DATA inputs must be complementary waveforms, of 50% duty cycle average, with no gate delays between them.