CXK77V3211Q

Features:

• Fast address access times and High frequency operation

• 5V tolerant inputs except I/O pins
• A FT pin for pipelined or flow-thru architecture
• A LBO mode pin as burst control pin(i486/Pentium™ and Linear burst sequence)
• Single +3.3V power supply
• Common data inputs and data outputs
• All inputs and outputs are LVTTL compatible
• Four Individual BYTE WRITE enables, GLOBAL WRITE and BYTE WRITE ENABLE
• Three Chip Enables for simple depth expansion
• One cycle output disable for both pipelined and flow-thru operation
• Internal input registers for address, data and control signals
• Self-timed WRITE cycle
• Write pass through capability
• High 30pF output drive capability at rated access time
• A ZZ pin for powerdown
• 100-lead QFP package for high density, high speed operation +10% 5%

Pinout

 

Description

The CXK77V3211Q is a 32K× 32 high performance synchronous SRAM with a 2-bit burst counter output register. All synchronous inputs pass through register controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable(CE), two additional chip enables for easy depth
expansion (CE2, CE2), burst control inputs (ADSC,ADSP, ADV), four individual byte write enables (BW1, BW2, BW3, BW4), one byte write enable (BWE), and global write enable (SGW).
Asynchronous inputs CXK77V3211Q include the output enable(OE) and power down control (ZZ). Two mode control pins (LBO, FT) define four different operation modes: Linear/Interleaved burst sequence and Flow-Thru/Pipelined operations.
WRITE cycles can be from one to four bytes wide as controlled by BW1 through BW4 and BWE or SGW. The output register is included on-chip and controlled by clock, it can be activated by connecting FT to high for high speed pipeline operation.
Burst operation can be initiated with either address status processor (ADSP) or address status controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV) CXK77V3211Q. Burst order sequence can be controlled by connecting LBO to high for Interleaved burst order (i486/Pentium™) or by connecting LBO to low for Linear burst order.
Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. WRITE pass through makes written data immediately available at the output register during READ cycle following a WRITE as controlled by OE.
The CXK77V3211Q operates from a +3.3V power supply and all inputs and outputs are LVTTL compatible. The device is ideally suited for i486 and Pentium™ systems and those systems which benefit from a very wide data bus.