CY2280

Features:

• Mixed 2.5V and 3.3V operation
• Clock solution for Pentium® II, and other similar processor-based motherboards
-Four 2.5V CPU clocks up to 100 MHz
-Eight 3.3V sync. PCI clocks, one free-running
-Two 3.3V 48-MHz USB clocks
-Three 3.3V Ref. clocks at 14.318 MHz
-Two 2.5V APIC clocks at 14.318 MHz or PCI/2
• EMI control
-Spread spectrum clocking
-Factory-EPROM programmable spread spectrum margin
-Factory-EPROM programmable output drive and slew rate
• Factory-EPROM programmable CPU clock frequencies for custom configurations
• Available in space-saving 48-pin SSOP package


Specifications

Supply Voltage.................................................0.5 to + 7.0V
Input Voltage............................................ 0.5V to VDD + 0.5
Storage Temperature (Non-Condensing) ... 65°C to +150°C
Junction Temperature............................................... +150°C
Package Power Dissipation.............................................. 1W
Static Discharge Voltage........................................... > 2000V


Description

The CY2280 is a Spread Spectrum clock synthesizer/driver for a Pentium II, or other similar processor-based PC requiring 100-MHz support. All of the required system clocks are provided in a space-saving 48-pin SSOP package. The CY2280 can be used with the CY231x for a total solution for systems with SDRAM.
The CY2280 provides the option of spread spectrum clocking on the CPU and PCI clocks for reduced EMI. A downspread percentage is introduced when the SEL_SS input is asserted.
The device can be run without spread spectrum when the SEL_SS input is deasserted. The percentage of spreading is EPROM-programmable to optimize EMI-reduction.
The CY2280 has power-down, CPU stop, and PCI stop pins for power management control. The signals are synchronized on-chip, and ensure glitch-free transitions on the outputs.
When the CPU_STOP input is asserted, the CPU clock outputs are driven LOW. When the PIC_STOP input is asserted, the PCI clock outputs (except the free-running PCI clock) are driven LOW. When the PWR_DWN pin is asserted, the reference oscillator and PLLs are shut down, and all outputs are driven LOW.