CY26049-36

Features: • Fully integrated phase-locked loop (PLL)• FailSafe output• PLL driven by a crystal oscillator that is phase aligned with external reference• Output frequencies selectable and/or programmed to standard communication frequencies• Low-jitter, high-acc...

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SeekIC No. : 004319200 Detail

CY26049-36: Features: • Fully integrated phase-locked loop (PLL)• FailSafe output• PLL driven by a crystal oscillator that is phase aligned with external reference• Output freque...

floor Price/Ceiling Price

Part Number:
CY26049-36
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/22

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Product Details

Description



Features:

• Fully integrated phase-locked loop (PLL)
• FailSafe output
• PLL driven by a crystal oscillator that is phase aligned with external reference
• Output frequencies selectable and/or programmed to standard communication frequencies
• Low-jitter, high-accuracy outputs
• Commercial and Industrial operation
• 3.3V ± 5% operation
• 16-lead TSSOP



Pinout

  Connection Diagram


Specifications

Supply Voltage (VDD) ........................................0.5 to +7.0V
DC Input Voltage........................................ 0.5V to VDD+0.5
Storage Temperature (Non-Condensing) ....55°C to +125°C
Junction Temperature ................................ 40°C to +125°C
Data Retention @ Tj=125°C...................................>10 years
Package Power Dissipation...................................... 350 mW
ESD (Human Body Model) MIL-STD-883.................... 2000V
(Above which the useful life may be impaired. For user guidelines,
not tested.



Description

CY26049 is a FailSafe frequency synthesizer with a reference clock input and three clock outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. The  continuous, glitch-free operation is achieved by using a DCXO which serves as a primary clock source. The FailSafe control circuit synchronizes the DCXO with the reference as long as the reference is within the pull range of the crystal.

In the event of a reference clock failure the DCXO maintains the last frequency and phase information of the reference clock. The unique feature of the CY26049-36 is that the DCXO is in fact the primary clocking source. When the reference clock is restored, the DCXO automatically re-synchronizes to the reference. The status of the reference clock input, as detected by the CY26049-36, is reported by the SAFE pin.

In the buffer mode (FS3:FS0 = 1110 or 1111), the CY26049-36 can be used as a jitter attenuator. In this mode, extensive jitter on the input clock will be "filtered", resulting in a low-jitter output clock.




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