CY2CC1810

Features: • Low-voltage operation• VDD range from 2.5 to 3.3V• 1:10 fanout• Drives either a 50-ohm or 75-ohm transmission line• Over voltage tolerant input hot swappable• Low input capacitance• Low output skew• Low propagation delay• Typical (t...

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SeekIC No. : 004319280 Detail

CY2CC1810: Features: • Low-voltage operation• VDD range from 2.5 to 3.3V• 1:10 fanout• Drives either a 50-ohm or 75-ohm transmission line• Over voltage tolerant input hot swappabl...

floor Price/Ceiling Price

Part Number:
CY2CC1810
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/11

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Product Details

Description



Features:

• Low-voltage operation
• VDD range from 2.5 to 3.3V
• 1:10 fanout
• Drives either a 50-ohm or 75-ohm transmission line
• Over voltage tolerant input hot swappable
• Low input capacitance
• Low output skew
• Low propagation delay
• Typical (tpd < 4 ns)
• High-speed operation > 200 MHz
• LVTTL-/LVCMOS-compatible input
       -Output disable to three-state
• Industrial versions available
• Packages available include: SOIC/SSOP



Pinout

  Connection Diagram


Specifications

Storage Temperature: .....................................................65°C to + 150°C
Ambient Temperature:.........................................................40°C to +85°C
Supply Voltage to Ground Potential VCC................................. 0.5V to 4.6V
Input ...................................................................................... 0.5V to 5.8V
Supply Voltage to Ground Potential (Outputs only) ..... 0.5V to VDD + 0.5V
DC Output Voltage........................................................ 0.5V to VDD + 0.5V
Power Dissipation............................................................................... 0.75W




Description

The Cypress series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industries fastest logic and buffers.

The Cypress CY2CC1810 fanout buffer features one input and ten three-state outputs.

Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock.

AVCMOS-type outputs dynamically adjust for variable impedance-matching and eliminate the need for seriesdamping resistors; they also reduce noise overall.




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