CY2DL814

• Low-voltage operation
• V_DD = 3.3V
• 1:4 Fanout
• Single-input configurable for:
         LVDS, LVPECL, or LVTTL
         Four differential pairs of LVDS outputs
• Drives 50- or 100-ohm load (selectable)
• Low input capacitance
• Low output skew
• Does not exceed Bellcore 802.3 standards
• Operation at ⇒ 350 MHz 700 Mbps
• Low propagation delay Typical (tpd < 4 ns)
• Industrial versions available
• Packages available include TSSOP/SOIC

Storage Temperature: .................................................................65°C to + 150°C
Ambient Temperature:.....................................................................40°C to +85°C
Supply Voltage to Ground Potential (Inputs and V_CC only)................... 0.3V to 4.6V
Supply Voltage to Ground Potential (Outputs only) .................... 0.3V to V_DD + 0.3V
DC Input Voltage ........................................................................ 0.3V to V_DD + 0.3V
DC Output Voltage....................................................................... 0.3V to V_DD + 0.9V
Power Dissipation.............................................................................................. 0.75W

The Cypress CY2 series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industry's fastest logic.

The Cypress CY2DL814 fanout buffer features a single LVDS-, LVPECL-, or LVTTL-compatible input and four LVDS output pairs.

Designed for data-communication clock management applications, the fanout from a single input reduces loading on the input clock.

The CY2DL814 is ideal for both level translations from single ended to LVDS and/or for the distribution of LVDS-based clock signals. The Cypress CY2DL814 has configurable input and output functions. The input can be selectable for LVPECL/LVTTL or LVDS signals while the output driver's support standard and high drive LVDS. Drive either a 50-ohm or 100-ohm line with a single part number/device.