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CY2DP818-2

Features: • Low-voltage operation VDD = 3.3V• 1:8 fanout• Single-input-configurable for LVDS, LVPECL, or LVTTL• 8 pairs of LVPECL outputs with enable/disable• Drives a 50-ohm load• Low input capacitance• Low output skew• Low propagation delay Typical...

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CY2DP818-2: Features: • Low-voltage operation VDD = 3.3V• 1:8 fanout• Single-input-configurable for LVDS, LVPECL, or LVTTL• 8 pairs of LVPECL outputs with enable/disable• Drives a ...

CY2DP818-2 Data Sheet

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Part Number:
CY2DP818-2
Supply Ability:
5000

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  • 1~5000
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Product Details

Description



Features:

• Low-voltage operation VDD = 3.3V
• 1:8 fanout
• Single-input-configurable for LVDS, LVPECL, or LVTTL
• 8 pairs of LVPECL outputs with enable/disable
• Drives a 50-ohm load
• Low input capacitance
• Low output skew
• Low propagation delay Typical (tpd < 4 ns)
• Industrial versions available
• Package available include: TSSOP
• Does not exceed Bellcore 802.3 standards
• Operation up to 350 MHz/700 Mbps


Pinout

Connection Diagram


Specifications

Parameter Description Condition
Min.
Max.
Unit
VDD DC Supply Voltage Inputs and VCC
0.3
4.6
V
VDD DC Operating Voltage Outputs
0.3
VDD +0.3
V
VIN DC Input Voltage Relative to VSS, with or VDD applied
0.3
VDD +0.3
V
VOUT DC Output Voltage Relative to VSS
0.3
VDD + 0.9
V
VTT Output termination Voltage  
VDD ÷ 2
V
TS Temperature, Storage Non-functional
65
+150
°C
TA Temperature,Operating
Ambient		 Commercial Functional
0
70
°C
Industrial Functional
40
+85
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.


Description

This Cypress series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industry's fastest logic.

The Cypress CY2DP818-2 fanout buffer features a single LVDS or a single-ended LVTTL-compatible input and eight LVPECL output pairs.

Designed for data-communications clock-management applications, the large fanout from a single input reduces loading on the input clock.

The CY2DP818-2 is ideal for both level translations from single-ended to LVPECL and/or for the distribution of LVPECL-based clock signals.

The Cypress CY2DP818-2 has configurable input functions.

The input is user-configurable via the Inconfig pin for single ended or differential input.




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