CY2DP818

Features: • Low-voltage operation VDD = 3.3V• 1:8 fanout• Single-input-configurable for LVDS, LVPECL, or LVTTL• 8 pair of LVPECL outputs• Drives a 50-ohm load• Low input capacitance• Low output skew• Low propagation delay Typical (tpd < 4 ns)̶...

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SeekIC No. : 004319292 Detail

CY2DP818: Features: • Low-voltage operation VDD = 3.3V• 1:8 fanout• Single-input-configurable for LVDS, LVPECL, or LVTTL• 8 pair of LVPECL outputs• Drives a 50-ohm load• Lo...

floor Price/Ceiling Price

Part Number:
CY2DP818
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/26

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Product Details

Description



Features:

• Low-voltage operation VDD = 3.3V
• 1:8 fanout
• Single-input-configurable for LVDS, LVPECL, or LVTTL
• 8 pair of LVPECL outputs
• Drives a 50-ohm load
• Low input capacitance
• Low output skew
• Low propagation delay Typical (tpd < 4 ns)
• Industrial versions available
• Package available include: TSSOP
• Does not exceed Bellcore 802.3 standards
• Operation at ⇒ 350 MHz700 Mbps



Pinout

  Connection Diagram


Specifications

Storage Temperature: .............................................................65°C to + 150°C
Ambient Temperature:.................................................................40°C to +85°C
Supply Voltage to Ground Potential (Inputs and VCC only)............ 0.3V to 4.6V
Supply Voltage to Ground Potential (Outputs only) ............ 0.3V to VDD + 0.3V
DC Input Voltage ................................................................ 0.3V to VDD + 0.3V
DC Output Voltage............................................................... 0.3V to VDD + 0.9V
Power Dissipation...................................................................................... 0.75W




Description

This Cypress series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industry's fastest logic.

The Cypress CY2DP818 fanout buffer features a single LVDS or a single-ended LVTTL-compatible input and eight LVPECL output pairs.

Designed for data-communications clock-management applications, the large fanout from a single input reduces loading on the input clock.


The CY2DP818 is ideal for both level translations from single-ended to LVPECL and/or for the distribution of LVPECL-based clock signals.

The Cypress CY2DP818 has configurable input functions. The input is user configurable via the Inconfig pin for single ended or differential input.




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