Features: `Function, Pinout, and Drive Compatible With FCT, F, and AM29841 Logic`Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions`Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics`Ioff Supports Partial-Power-Down Mode Operation`Matched Rise and Fall T...
CY74FCT841T: Features: `Function, Pinout, and Drive Compatible With FCT, F, and AM29841 Logic`Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions`Edge-Rate Control Circuitry for Significantly Im...
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US $.61 - .92 / Piece
Encoders, Decoders, Multiplexers & Demultiplexers 1-of-8 Decoder
US $.42 - .46 / Piece
Encoders, Decoders, Multiplexers & Demultiplexers 1-OF-8 DECODER
US $.42 - .46 / Piece
Encoders, Decoders, Multiplexers & Demultiplexers 1-of-8 Decoder
Supply voltage range to ground potential . . . . . . . . . . . . . 0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . .120 mA
Package thermal impedance, JA (see Note 1): P package . . . .67°C/W
(see Note 2): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
(see Note 2): SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Ambient temperature range with power applied, TA . . 65°C to 135°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . 65°C to 150°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
The 'FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing latches and provide additional data width for wider address/data paths or buses carrying parity. The 'FCT841T devices are buffered 10-bit-wide versions of the FCT373 function.
The 'FCT841T devices' high-performance interface is designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.
FCT841T is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.